Memory System With Parallel Dummy Reads Before Patrol Reads

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Solution Overview

Problem

The existing memory systems require significant time for patrol read operations due to the serial execution of dummy and unit read commands, which can be optimized to reduce overall read operation time.

Innovation Solution

The bridge chip is configured to generate and execute dummy read operations in parallel for multiple memory chips, independent of the host channel availability, thereby reducing the time required for patrol read operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If dummy read operations and unit read operations are executed serially, then the memory system can maintain simple control logic, but the overall read operation time increases significantly

Engineering Contradiction:

Improveread operation timeVSAvoidcontrol logic complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The bridge chip executes dummy read operations in advance before the host controller issues unit read commands. By performing these preliminary actions locally at the bridge chip without waiting for host controller instructions, the system reduces the overall time required for patrol read operations while maintaining manageable control complexity through automated bridge chip functionality

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The read operation process is divided into two independent segments: dummy read operations executed by the bridge chip for status checking, and unit read operations executed by the host controller for data retrieval. This segmentation allows both operations to proceed in parallel without interfering with each other, significantly reducing total read operation time

Inventive Principle:

Principle #1Segmentation

2Productivity

If the bridge chip executes dummy read operations independently without host channel availability check, then the read operation time is reduced, but the complexity of coordinating multiple memory chips increases

Engineering Contradiction:

Improvepatrol read operation speedVSAvoidbridge chip control complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The bridge chip autonomously manages the execution of dummy read operations on multiple memory chips without requiring continuous coordination or availability checks from the host controller. Each bridge chip independently determines when to execute dummy reads based on its own internal state and memory chip status, enabling parallel operations while keeping control complexity localized to individual bridge chips rather than requiring system-wide coordination

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS12461690B2Memory system with dummy read before patrol read

Publication Date: 2025.11.04 KIOXIA CORP

AI summary

According to one embodiment, a semiconductor integrated circuit, also referred to as a bridge chip or circuit, has a first interface circuit configured to be connected to a control device and a second interface circuit configured to be connected to a memory chip. A controller in the integrated circuit is configured to transfer a first command sequence for commanding a dummy read operation on a storage region of the memory chip via the second interface circuit before executing a patrol read operation on the storage region of the memory chip based on a request from the control device received via the first interface circuit.