Semiconductor Memory Device Parallel Read Voltage Application
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Solution Overview
Problem
Current NAND-type flash memory devices face challenges in efficiently storing and retrieving 8-bit data due to limitations in the number of read operations per memory cell transistor, leading to reduced storage capacity and increased read times.
Innovation Solution
The semiconductor memory device employs a combination of two memory cell transistors to store 8-bit data, utilizing a unique threshold voltage distribution and share coding scheme that allows for parallel application of read voltages across word lines, enabling faster and more efficient read operations across multiple pages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single memory cell transistor is used to store data, then the device complexity is reduced, but the storage capacity and read operation efficiency are limited
Solution Approach 1:
The patent combines two memory cell transistors (first memory cell transistor MTa and second memory cell transistor MTb) to store 8-bit data, achieving higher storage capacity while managing complexity through a coordinated read operation system that processes both transistors in parallel
2Productivity
If sequential read operations are performed on memory cell transistors, then the read operation time increases, but the storage capacity per cell remains limited
Solution Approach 1:
The patent implements parallel read operations where the controller simultaneously applies read voltages to both the first memory cell transistor MTa and second memory cell transistor MTb, enabling continuous and efficient data retrieval without sequential delays
Solution Approach 2:
The patent introduces a multi-dimensional read voltage application system that can apply different read voltages (first read voltage and second read voltage) to different transistors simultaneously, adding a temporal and spatial dimension to the read operation for improved throughput
3Quantity of substance
If multiple read operations are performed per memory cell transistor to increase storage capacity, then the read operation speed decreases, but the storage capacity increases
Solution Approach 1:
The controller is configured to apply read voltages to both memory cell transistors in advance and in parallel during the read operation, preparing the data retrieval path beforehand so that multiple data bits can be read simultaneously without sequential delays
Data Source
AI summary
A semiconductor memory device according to an embodiment includes first memory cells, second memory cells, and a controller. A threshold voltage of each of the first memory cells and the second memory cells is included in one of first through sixteenth state. 8-bit data that includes a first through eighth bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell. The controller is configured to: apply in parallel a plurality of types of read voltages to each of the first memory cells and the second memory cells and externally output data confirmed based on first data read from the first memory cells and second data read from the second memory cells.