Semiconductor Memory Testing via Parallel Data Transfer and Comparison
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Solution Overview
Problem
As semiconductor memory apparatuses increase in data storage capacity, the time required for testing them also increases, necessitating a more efficient method to verify their functionality.
Innovation Solution
A semiconductor memory apparatus is designed with input/output pads, data transfer circuits, and test data comparison circuits that allow for simultaneous data storage and transfer across multiple chips, enabling efficient testing by comparing data across different storage regions and transfer circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data storage capacity is increased, then storage capacity is improved, but test time is increased
Solution Approach 1:
The patent divides the testing process into parallel segments by using multiple data storage regions (first and second data storage regions) that can be tested simultaneously. The data transfer circuits are also segmented into multiple independent paths, allowing concurrent testing of different data regions without sequential delays.
Solution Approach 2:
The patent implements preliminary action by pre-configuring multiple data storage regions and transfer circuits before testing begins. The test data comparison circuit is prepared in advance to compare data from multiple regions simultaneously, eliminating the need for sequential testing operations.
2Reliability
If multiple data storage regions are tested sequentially, then testing thoroughness is improved, but test time is increased
Solution Approach 1:
The patent ensures continuity of useful action by enabling simultaneous testing of multiple data storage regions through parallel data transfer circuits. The test data comparison circuit continuously compares data from all regions without interruption or sequential delays, maintaining constant testing throughput.
Solution Approach 2:
The patent merges multiple testing operations into a single unified testing process. Data from multiple storage regions are transferred and compared simultaneously through integrated data transfer circuits and a unified test data comparison circuit, combining what would traditionally be separate sequential tests into one parallel operation.
3Ease of operation
If data transfer and comparison operations are performed separately, then operational simplicity is improved, but testing efficiency is reduced
Solution Approach 1:
The test data comparison circuit serves multiple functions simultaneously: it compares data from multiple storage regions, validates data integrity across different transfer paths, and generates comprehensive test results. This multi-functionality eliminates the need for separate comparison operations for each data region.
Solution Approach 2:
The system performs preliminary data gathering and preparation in parallel across multiple transfer circuits, so that when comparison is needed, all data is already ready simultaneously. This preliminary parallel preparation eliminates sequential bottlenecks in the testing process.
Data Source
AI summary
A semiconductor memory apparatus includes an input/output pad, a first data input/output circuit, a first data transfer circuit, a second data transfer circuit, and a test data comparison circuit. The input/output pad may be coupled to an external equipment. The first data input/output circuit may be coupled to the input/output pad. The first data transfer circuit may transfer data output from the first data input/output circuit to a first data storage region in response to a test write signal and transfer data output from the first data storage region to the first data input/output circuit in response to a test read signal. The second data transfer circuit may transfer data output from the first data input/output circuit to a second data storage region in response to the test write signal and transfer data output from the second data storage region to a second data input/output circuit in response to the test read signal. The test data comparison circuit may generate a test result signal by comparing data output from the first data storage region, the second data storage region, the first data transfer circuit, and the second data transfer circuit and output the test result signal to the external equipment through the input/output pad.