Memory Device Parallel Verify Operation
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Solution Overview
Problem
Current semiconductor memory devices face inefficiencies in programming speed due to the need for multiple verify operations with different voltages, which increases time and complexity.
Innovation Solution
A memory device and operating method that simultaneously perform verify operations for multiple program states by applying bit line voltages with different voltage levels to memory cells, allowing for concurrent verification and reduced programming time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple verify operations with different voltages are performed sequentially, then verification accuracy is improved, but programming time increases
Solution Approach 1:
The patent combines multiple verify operations that were previously performed sequentially into a single simultaneous verify operation. By applying different voltage levels to different bit lines at the same time, the system verifies multiple program states concurrently, reducing total verification time while maintaining accuracy.
Solution Approach 2:
The patent transitions from sequential verification (one dimension in time) to parallel verification by introducing a voltage level dimension. Different bit lines receive different voltage levels simultaneously, enabling multi-dimensional verification that reduces time loss while preserving measurement precision.
2Reliability
If multiple verify operations with different voltages are performed, then verification completeness is improved, but operational complexity increases
Solution Approach 1:
The patent creates a universal verify operation that can handle multiple program states simultaneously. The same verify operation circuit and control logic are used to verify different program states by simply applying different voltage levels to different bit lines, making the system multi-functional without increasing hardware complexity.
Solution Approach 2:
The patent changes the voltage level parameter of bit lines to differentiate between different program state verifications. Instead of using separate circuits or complex control mechanisms, the system varies the voltage level parameter to achieve verification completeness across multiple states while keeping the operational structure simple.
3Device complexity
If sequential verify operations are performed, then control simplicity is maintained, but programming speed decreases
Solution Approach 1:
The patent introduces dynamic voltage level assignment to bit lines during the verify operation. The control logic dynamically assigns different voltage levels to different bit lines based on the program state being verified, enabling parallel verification while maintaining relatively simple control structures. This dynamic parameter adjustment increases programming speed without significantly increasing device complexity.
Data Source
AI summary
A memory device having an improved program speed may include a memory cell array including a plurality of memory cells, each being programmed to one of a plurality of program states; a peripheral circuit configured to perform a program operation to one or more of the plurality of memory cells, the program operation including a program voltage applying operation and a verify operation; and a control logic configured to control the peripheral circuit to simultaneously perform the verify operation for at least two program states by applying bit line voltages having different voltage levels to bit lines coupled to the plurality of memory cells.