Memory Sub-Module Parallel Writing for Shorter Programming Time

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Solution Overview

Problem

Existing data writing methods for rewritable non-volatile memory modules are inefficient due to sequential writing in both first and second areas, leading to reduced writing efficiency and inability to write both areas simultaneously, which increases programming time.

Innovation Solution

A data writing method that uses a first programming mode to write data into first physical programming units of one memory sub-module and a second programming mode to write remaining data into a different second memory sub-module, allowing for parallel writing and reducing programming time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If sequential writing mode is used for both first and second areas, then data can be written into memory sub-modules in order, but writing efficiency is reduced and programming time is increased

Engineering Contradiction:
Improvewriting efficiencyVSAvoidprogramming time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent divides the writing process into two independent segments: first area writing and second area writing. Each area can be written independently using different programming modes simultaneously, rather than sequentially. This segmentation allows parallel execution of writing operations, improving productivity and reducing total programming time.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from one-dimensional sequential writing to two-dimensional parallel writing by utilizing both first and second areas across multiple memory sub-modules simultaneously. This dimensional expansion enables concurrent writing operations, resolving the contradiction between writing efficiency and programming time.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of operation

If first area and second area are written independently without coordination, then each area can be processed separately, but simultaneous writing capability is lost

Engineering Contradiction:
Improveindependent processing capabilityVSAvoidsimultaneous writing capability
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent merges the independent writing operations of first and second areas into a coordinated parallel processing system. By combining the independence of each area with simultaneous execution capability, the system achieves both ease of operation and improved productivity through coordinated parallel writing.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10529426B2Data writing method, valid data identifying method and memory storage apparatus
Publication Date: 2020.01.07 PHISON ELECTRONICS
  • US10529426B2 patent drawing
  • US10529426B2 patent drawing
  • US10529426B2 patent drawing

AI summary

A data writing method, a valid data identifying method and a memory storage apparatus using the same are provided. The method includes receiving first data; using a first programming mode to write first sub-data of the first data into a first physical programmed unit of at least a first memory sub-module of a plurality of memory sub-modules, wherein a size of each of the first sub-data is the same as a preset size; and using a second programming mode to write remaining sub-data of the first data into a second physical programmed unit of a second memory sub-module of the plurality of memory submodules, wherein the size of the remaining sub-data is less than the preset size, and the second memory sub-module is different from a third memory sub-module of the first memory submodules which is a last memory sub-module for writing the first sub-data.