Memory Parity Circuit for Fast 2-Bit Error Detection
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Solution Overview
Problem
Existing MCU systems face challenges in detecting 2-bit errors during high-speed operation, as current error correcting circuits are complex and not suitable for high-speed pipelines, leading to erroneous determinations and inability to detect 2-bit errors, which is critical for ensuring functional safety in applications like Advanced Driver Assistance Systems.
Innovation Solution
A data processing apparatus with a parity generating circuit that generates parity for multiple bits and a parity/ECC decoder circuit capable of detecting one-bit or two-bit errors, allowing for error detection prior to the error correction process, thereby enabling high-speed operation and accurate error detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional 1-bit error correction/2-bit error detection (SEC-DED) circuit is used, then error detection capability is provided, but the circuit becomes complex and unsuitable for high-speed operation
Solution Approach 1:
The patent segments the error detection function into two independent parts: a simple parity check circuit for 1-bit error detection and a separate 2-bit error detection circuit. This segmentation allows each circuit to be optimized independently, with the parity check providing fast 1-bit detection and the dedicated 2-bit detection circuit providing comprehensive error coverage without requiring a complex SEC-DED implementation.
Solution Approach 2:
The patent introduces an intermediary 2-bit error detection circuit that works in conjunction with the parity check. This intermediary component specifically targets the limitation of traditional parity checks (inability to detect 2-bit errors) while maintaining circuit simplicity. The intermediary circuit processes the same data bits and provides additional error detection capability without replacing the entire error detection system.
2Reliability
If error correction processing is performed when an error is detected, then error correction is achieved, but the pipeline is stalled and high-speed operation is compromised
Solution Approach 1:
The patent performs preliminary error detection using simple parity checks before data is written to or read from memory. By detecting errors early in the data flow and using dedicated detection circuits that operate in parallel with the main data path, the system can identify errors without stalling the pipeline. The preliminary detection allows the system to maintain high-speed operation while ensuring error correction capability through separate correction mechanisms.
3Productivity
If a simple parity check is used for error detection, then high-speed operation is maintained, but 2-bit errors cannot be detected
Solution Approach 1:
The patent creates a multi-functional error detection system where the parity check circuit handles 1-bit error detection and the additional 2-bit error detection circuit handles both 1-bit and 2-bit error detection. This universal approach allows the system to detect various types of errors using a coordinated set of circuits rather than requiring a single complex SEC-DED circuit, thereby maintaining high-speed operation while improving reliability.
Data Source
AI summary
A data processing apparatus includes a memory, a processor which outputs write data when making a write request to the memory, and which inputs read data when making a read request to the memory, a parity generating circuit which generates a parity comprising a plurality of parity bits from the write data, the parity being written with the write data into the memory, and a parity check circuit which is coupled between the memory and the processor, and which detects a presence or absence of an error of one bit or two bits in the read data and the parity read from the memory, wherein the parity generating circuit generates the parity so that at least one of a first write data bit and a second write data bit included in the write data contributes to generation of at least two parity bits.