Memory Parity Block Placement for Bad Group Detection
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Solution Overview
Problem
Existing memory systems face data loss due to failures in memory devices or blocks, particularly when using parity stripes, which can lead to unnecessary reduction in available memory capacity and inefficiencies in error detection.
Innovation Solution
The method involves determining the location of error detection data based on the location of bad memory groups within a memory system, allowing for the storage of error detection data in a way that prioritizes data integrity by placing parity blocks strategically across multiple memory units, ensuring that valid data is written after parity blocks to prevent loss in case of failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity stripes are used for error detection, then data integrity is improved, but available memory capacity is reduced
Solution Approach 1:
The patent applies local quality by placing parity blocks specifically in blocks that contain bad memory groups, rather than uniformly across all blocks. This targeted approach ensures error detection capability is concentrated where needed (in blocks with bad groups) while minimizing the overall impact on available memory capacity.
Solution Approach 2:
The patent performs preliminary action by identifying bad memory groups before creating parity stripes. The system scans memory blocks, detects bad groups, and uses this information to strategically determine where to place parity blocks, ensuring that parity protection is applied proactively to vulnerable areas before data storage operations commence.
2Reliability
If parity blocks are placed in all blocks, then error detection coverage is improved, but memory efficiency deteriorates
Solution Approach 1:
The patent implements local quality by making the presence of parity blocks location-dependent. Specifically, parity blocks are placed only in blocks that contain bad memory groups, rather than in all blocks uniformly. This creates a non-uniform distribution that optimizes error detection coverage in vulnerable areas while maintaining memory efficiency in healthy areas.
Solution Approach 2:
The patent applies partial action by providing parity protection only where necessary (in blocks with bad groups) rather than applying it universally. This partial approach achieves sufficient error detection coverage for the system's reliability requirements while avoiding the excessive overhead that would result from placing parity blocks in all blocks.
3Reliability
If traditional parity stripe methods are used, then error detection capability is maintained, but adaptability to bad blocks deteriorates
Solution Approach 1:
The patent applies dynamics by making the parity stripe creation process adaptive rather than static. The system dynamically adjusts parity block placement based on the actual condition of memory blocks, specifically identifying and responding to bad memory groups. This dynamic approach allows the system to adapt its error detection strategy to the specific characteristics of each block.
Solution Approach 2:
The patent implements parameter changes by modifying the parity stripe creation parameters based on block quality. Specifically, the system changes the placement parameter (where parity blocks are located) based on the detected presence of bad memory groups, transforming a fixed parameter approach into a variable one that responds to actual memory conditions.
Data Source
AI summary
Methods, devices, and systems for determining location of error detection data are described. One method for operating a memory unit having a bad group of memory cells includes determining a location of where to store error detection data for data to be stored across a plurality of memory units, including the memory unit having the bad group, based at least partially on a location of the bad group and storing the error detection data in the determined location.