Memory Controller Parity Buffer for Incomplete NAND Flash Writes
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Solution Overview
Problem
Existing memory controllers for NAND flash memory struggle with efficient error correction when the amount of write-data is less than the predetermined size, leading to incomplete parity generation and storage, which affects data reliability during read operations.
Innovation Solution
A memory controller that includes an encoder for calculating parity, a parity buffer for storing both completed and intermediate parity, and a decoder for performing decoding processes based on input data size and read requests, ensuring error correction even when parity is not fully written to the non-volatile memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data is written in units less than a predetermined size, then writing flexibility is improved, but error correction capability deteriorates due to insufficient parity data
Solution Approach 1:
The patent applies preliminary action by calculating and storing intermediate parity data during the writing process before the data is fully written. The parity buffer stores this intermediate parity information, which can be later retrieved and used for error correction even when the data writing is incomplete, thus resolving the contradiction between writing flexibility and error correction capability
Solution Approach 2:
The patent introduces an intermediary mechanism - the parity buffer - that stores intermediate parity data calculated during the writing process. This intermediary storage allows the system to perform error correction using partial parity information when data is not fully written, thereby maintaining error correction capability while allowing flexible writing units
2Reliability
If intermediate parity is stored in a parity buffer, then error correction for incomplete data is improved, but device complexity increases
Solution Approach 1:
The parity buffer serves multiple functions: it stores intermediate parity during writing, preserves it for incomplete writes, and provides data for both inter-page and inner-page decoding. This multi-functionality reduces the need for separate dedicated storage structures, thereby limiting the increase in device complexity while improving error correction capability
3Reliability
If iterative decoding using both inter-page and inner-page parity is performed, then data integrity is improved, but processing time increases
Solution Approach 1:
The patent applies dynamics by implementing a conditional iterative decoding process that adapts to the data writing status. The controller determines whether to perform inter-page decoding, inner-page decoding, or both based on whether data is fully written or incomplete. This dynamic approach ensures data integrity through comprehensive error correction while minimizing unnecessary processing time by avoiding redundant decoding steps
Data Source
AI summary
According to one embodiment, a memory controller according to the embodiments includes an encoder that sequentially calculates parity based on data; a parity buffer that stores completed parity and intermediate parity based on data less than a predetermined size; a write processing unit that writes data and completed parity on a non-volatile memory; a decoder; and a controller that performs a decoding process based on the data read from the non-volatile memory and the intermediate parity in the parity buffer, when receiving a read request to inputted data in a stage in which the a number of inputted data to the encoder is less than the predetermined size.