Memory Module Parity Architecture for Variable Burst Error Correction
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Solution Overview
Problem
Current memory systems lack efficient error detection and correction mechanisms, particularly in handling data sets of varying burst lengths, which can lead to errors during data transmission and storage, affecting reliability and availability.
Innovation Solution
The implementation of a memory module with multiple data memories and a parity memory, where each data memory has regions for storing data sets and parity bits, and the parity memory has regions for storing parity bits associated with user data sets, utilizing a cyclic redundancy check generator and parity generator to ensure error detection and correction across multiple burst lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error detection mechanisms are used in memory systems, then error detection capability is provided, but the system lacks efficiency in handling data sets of varying burst lengths and requires additional CRC memory and lockstep configurations
Solution Approach 1:
The parity memory device is designed to perform multiple functions: it generates parity bits for data sets of various burst lengths (8, 16, 32, 64 bytes) and performs error detection and correction. The single parity memory device replaces what would traditionally require separate CRC memory and lockstep configurations, making the system more universal and less complex
Solution Approach 2:
The system dynamically adapts to different burst lengths (8, 16, 32, 64 bytes) by changing operational parameters rather than requiring separate hardware configurations for each burst length. The parity memory device can handle variable burst lengths through parameter adjustments, eliminating the need for additional specialized memory components
2Quantity of substance
If the number of data memories is increased to improve storage capacity, then storage volume is improved, but error detection and correction becomes more difficult without additional configurations
Solution Approach 1:
The parity memory device acts as an intermediary between multiple data memories (first through fourth data memories) and the memory controller. It receives data from multiple sources, generates appropriate parity bits, and provides error detection and correction capabilities that protect data from all data memories without requiring complex interconnections or additional configuration for each memory pair
3Ease of manufacture
If traditional memory module configurations are used, then manufacturing is simpler, but error detection and correction efficiency is reduced for varying burst lengths
Solution Approach 1:
The memory module is segmented into distinct functional components: multiple data memories (first through fourth) and a separate parity memory device. This segmentation allows each component to be optimized independently - data memories for storage and the parity memory for error detection/correction - while maintaining relatively simple manufacturing processes. The modular design preserves ease of manufacture while significantly improving error detection efficiency
Data Source
AI summary
A memory module includes data memories and at least one parity memory. Each of the data memories includes a first memory cell array with a first memory region to store data set corresponding to a plurality of burst lengths and a second memory region to store first parity bits to perform error detection/correction associated with the data set. The at least one parity memory includes a second memory cell array with a first parity region to store parity bits associated with user data set corresponding to all of the data set stored in each of the data memories and a second parity region to store second parity bits for error detection/correction associated with the parity bits.