Memory Parity Column Layout for ECC Bit-Line Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor memory devices are inefficient in storing parity bits, as they often require a fixed number of bit lines per column plane, leading to unnecessary space usage and increased memory cell count, especially when using single error correction (SEC) implementations.
Innovation Solution
The proposed solution involves a semiconductor device with a memory array organized into data and parity column planes, where the number of bit lines accessed in parity column planes can differ from those in data column planes, allowing for a more efficient match between the number of accessed parity bits and the error correction circuit's requirements, thereby reducing the number of memory cells needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a fixed number of bit lines per column plane is used in conventional memory devices, then the memory structure is simple and easy to manufacture, but the number of memory cells increases unnecessarily and space is wasted
Solution Approach 1:
The memory array is segmented into separate data column planes and parity column planes, each with different numbers of bit lines. Data column planes have a first number of bit lines while parity column planes have a second number of bit lines, allowing each segment to be optimized for its specific function rather than using a uniform structure throughout.
Solution Approach 2:
Different parts of the memory array are given different properties: data column planes are configured with a specific number of bit lines optimized for data storage, while parity column planes are configured with a different number of bit lines optimized for parity bit storage and error correction functionality.
2Reliability
If more parity bits are stored in the array to enhance error correction capability, then error detection and correction capability improves, but the number of memory cells and device size increases
Solution Approach 1:
The patent uses parity bits as a form of redundant information copied from the data, stored in separate parity column planes. These parity bits are generated from the data bits and used to detect and correct errors without requiring additional full memory cells, effectively using a compressed form of redundancy.
3Ease of manufacture
If the number of bit lines in parity column planes is increased to match data column planes, then the memory structure is uniform and easier to manufacture, but the number of accessed parity bits exceeds what is needed for error correction
Solution Approach 1:
The system dynamically adjusts the number of bit lines accessed in parity column planes based on the actual error correction requirements. The column select signal is configured to access a second number of bit lines in parity column planes that is optimized for the error correction capability needed, rather than always accessing a fixed number matching the data column planes.
4Quantity of substance
If fewer parity bits are stored to reduce memory cell count, then device size decreases, but the error detection and correction capability is reduced
Solution Approach 1:
The patent changes the parameters of the parity column planes, specifically the number of bit lines (second number) to be different from the data column planes (first number). This parameter change allows the system to store an optimized number of parity bits that provides adequate error correction capability while minimizing the number of memory cells required.
Data Source
AI summary
Apparatuses and methods for on-device error correction implemented in a memory. A memory may have a first column plane comprising a first number of bit lines and a parity column plane that has a second number of parity bit lines in which the first number is different than the second number. In an access operation, a column select signal may activate the first number of bit lines in the first column plane and the second number of parity bit lines in the second column plane.