Memory Channel Parity Compression for Faster SSD Reads

Solution Overview

Problem

Solid-state drives (SSDs) face a bottleneck in data channel communication, leading to reduced response time and efficiency due to high latency and throughput issues, especially in client SSDs and mobile NVM systems with small instruction queues.

Innovation Solution

A memory system that includes a data channel and a controller configured to output requests, where the memory device generates and compresses a parity difference between loaded data and calculated parity, enabling the controller to access the data and compressed parity difference to satisfy requests, thereby reducing transmission time and improving latency and throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data and full parity are transmitted across the data channel, then error detection and correction capability is maintained, but transmission time increases and throughput decreases

Engineering Contradiction:

Improveerror detection and correction capabilityVSAvoidthroughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent extracts only the essential error correction information (parity difference) from the complete parity data and transmits it across the channel. The memory device calculates the difference between stored parity and newly calculated parity, compresses this difference, and transmits only the compressed parity difference along with data. The controller then reconstructs the full parity by combining the compressed parity difference with locally calculated parity, maintaining error correction capability while minimizing channel transmission volume.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the representation parameter of parity data from complete parity bits to compressed parity difference bits. By transforming the parity information into a differential format and applying compression algorithms, the amount of data transmitted across the channel is significantly reduced, directly improving throughput while preserving the ability to detect and correct errors through parity comparison.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If data and full parity are transmitted across the data channel, then error detection and correction capability is maintained, but latency increases

Engineering Contradiction:

Improveerror detection and correction capabilityVSAvoidlatency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts only the essential error correction information (parity difference) from the complete parity data and transmits it across the channel. The memory device calculates the difference between stored parity and newly calculated parity, compresses this difference, and transmits only the compressed parity difference along with data. The controller then reconstructs the full parity by combining the compressed parity difference with locally calculated parity, maintaining error correction capability while minimizing channel transmission volume.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the representation parameter of parity data from complete parity bits to compressed parity difference bits. By transforming the parity information into a differential format and applying compression algorithms, the amount of data transmitted across the channel is significantly reduced, directly improving throughput while preserving the ability to detect and correct errors through parity comparison.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If compressed parity difference is transmitted instead of full parity, then throughput improves and latency reduces, but device complexity increases

Engineering Contradiction:

ImprovethroughputVSAvoiddevice complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent performs preliminary compression of the parity difference at the memory device before transmission. By calculating the difference between stored parity and newly calculated parity, then compressing this difference using compression algorithms, the system prepares the data in an optimized format for channel transmission. This preliminary action reduces the burden on the channel and the controller, offsetting the added complexity at the memory device with simplified processing elsewhere in the system.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The compressed parity difference acts as an intermediary representation that bridges the memory device and controller. Instead of transmitting complete parity or raw data, the system uses this compressed differential form as an intermediate format that contains only the essential error correction information. This intermediary approach reduces transmission complexity while maintaining the ability to reconstruct full parity for error correction at the controller.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS10372534B2Method of operating memory device using a compressed party difference, memory device using the same and memory system including the device

Publication Date: 2019.08.06 SAMSUNG ELECTRONICS CO LTD

AI summary

A memory system includes a data channel, a controller configured to output a request across the data channel, and a memory device configured to store data and corresponding first parity, perform a decoding operation on the data to generate second parity in response to receipt of the request across the data channel, generate a difference from the first parity and the second parity, compress the difference, and enable the controller to access the data and the compressed difference to satisfy the request.