Multilevel Memory Error Detection via Parity Bit Copying
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Solution Overview
Problem
Existing multilevel memory systems face challenges in efficiently detecting and correcting errors across different memory levels, leading to potential data corruption and system crashes due to factors like radiation and electrical interference.
Innovation Solution
The proposed solution involves copying error detection parity bits from one memory level to another, eliminating the need for re-encoding parity bits at each level, which reduces delay and overhead. Additionally, active continuous diagnostic logic is implemented to monitor and correct errors in real-time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection parity bits are re-encoded at each memory level, then error detection capability is maintained, but processing delay and overhead increase
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing error detection parity bits at the first memory level before data transfer. These pre-computed parity bits are then copied to the second memory level, eliminating the need for re-encoding at the destination. This advance preparation resolves the contradiction by maintaining error detection capability while avoiding the time penalty of real-time re-encoding.
Solution Approach 2:
The patent directly applies the copying principle by replicating the pre-computed error detection parity bits from the first memory level to the second memory level. Instead of re-generating parity bits at each level, the system copies the existing valid parity bits, thereby maintaining error detection capability across memory levels without incurring the processing delay of re-encoding operations.
2Reliability
If robust fault detection is provided by having two or more processors operate in lock step, then fault detection capability is improved, but system size and cost increase significantly
Solution Approach 1:
The patent extracts the error detection function from the data processing path by separating parity bit generation from data transfer operations. The parity bits are generated independently in advance and copied along with the data, allowing error detection without requiring redundant processors operating in lock-step. This extraction resolves the contradiction by providing fault detection capability without the substantial increase in system size and cost that would result from duplicating entire processors.
3Reliability
If periodic interrupts are used to execute safety diagnostic routines, then fault detection is achieved, but system performance is impacted
Solution Approach 1:
The patent implements continuous error detection by copying parity bits with data during normal memory operations, rather than periodically interrupting execution for diagnostic routines. The error detection function operates continuously in the background as data is transferred between memory levels, eliminating performance penalties associated with periodic interrupts while maintaining reliable fault detection capability.
Data Source
AI summary
In described examples, a memory system is accessed by reading a data line and error detection bits for the data line from a first memory. The data line and the error detection bits from the first memory are decoded to determine if an error is present in the data line from the first memory. A copy of the data line and the error detection bits are stored in a second memory. The copy of the data line and error detection bits are read from the second memory. The copy of the data line and error detection bits are decoded to determine if an error is present in the copy of the data line from the second memory.