Memory Command Parity Signaling on Reused Data Pins
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Solution Overview
Problem
In memory systems, performing parity checking on command/address pins is challenging due to constraints on the number of pins available and varying timing requirements, making it impractical to use a dedicated pin for parity, especially when conveying a single bit of CA parity information.
Innovation Solution
The memory device utilizes data-associated pins like DMI, ECC, or RDQS, which are otherwise unused during command cycles, to convey CA parity information, allowing for parity checking without a dedicated pin, and logs the parity check result in a register.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated pin is used for CA parity checking, then parity checking capability is improved, but the number of available pins is reduced and device complexity increases
Solution Approach 1:
The patent applies multi-functionality by enabling data-associated pins (DMI, ECC, RDQS) to serve dual purposes: their primary data transfer function and a secondary function for conveying CA parity information during command cycles. This eliminates the need for dedicated parity pins while maintaining parity checking capability, thereby resolving the contradiction between reliability improvement and device complexity reduction
2Device complexity
If data-associated pins are used for CA parity conveying, then pin quantity is optimized, but timing constraints become more challenging
Solution Approach 1:
The patent implements preliminary action by conveying CA parity information during the command cycle itself, before the actual data transfer operations commence. This allows the memory device to prepare and communicate parity data in advance, ensuring that timing constraints are met while utilizing existing pin infrastructure for both command and parity purposes
3Productivity
If parity information is conveyed during unused pin cycles, then pin utilization is optimized, but signal interference may increase
Solution Approach 1:
The patent extracts CA parity information from the main data transfer stream and conveys it separately during unused portions of the command cycle on data-associated pins. This separation allows parity signaling to occur in isolated time windows without interfering with primary data operations, thus optimizing pin utilization while minimizing signal interference through temporal separation
Data Source
AI summary
Methods, systems, and devices for targeted command/address parity low lift are described. A memory device is configured to receive a command (e.g., a write command or a read command) from a host device over a first set of pins and is configured to perform data transfer over a second set of pins with the host device during a set of time intervals according to the command. The memory device is configured to exchange a parity bit associated with the command with the host device over a third set of pins during a first time intervals of the set of time intervals. In some cases, the third memory device is configured to exchange at least one additional bit associated with the command with the host device during at least one time interval of the set of time intervals.