Memory System Parity Data Reading for Deterministic Latency
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Solution Overview
Problem
Memory systems face challenges in providing deterministic latency for host devices due to the concurrent operations on nonvolatile memory devices, which can lead to inefficiencies and performance bottlenecks.
Innovation Solution
A memory system architecture that includes a first operation unit and one or more second operation units, where the first operation unit performs operations by reading target data and parity data from nonvolatile memory devices not associated with the second operations, allowing for parallel operation and prioritization of tasks to manage latency effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the first operation unit waits for the second operation unit to complete before performing operations on target data, then data integrity is ensured, but latency increases and deterministic performance cannot be guaranteed
Solution Approach 1:
The patent segments the memory system into multiple operation units (first operation unit and second operation unit) that can independently access different portions of target nonvolatile memory devices. This segmentation allows parallel operations where the first operation unit reads from portions not being accessed by the second operation unit, eliminating the need to wait for completion while maintaining data integrity.
Solution Approach 2:
The patent introduces a spatial dimension to the operation coordination by dividing the target nonvolatile memory devices into multiple portions that can be accessed simultaneously. Instead of temporal sequencing (one after another), the system uses spatial parallelism (different portions at the same time), allowing deterministic latency while ensuring data integrity through parity data validation.
2Productivity
If the memory system allows parallel operations on the same memory devices, then productivity increases, but conflicts arise and data integrity may be compromised
Solution Approach 1:
The patent divides the target nonvolatile memory devices into multiple portions that can be accessed in parallel by different operation units. The first operation unit is configured to read from portions not currently accessed by the second operation unit, enabling simultaneous operations without conflict while maintaining data integrity through the use of parity data for validation.
Solution Approach 2:
The patent uses parity data as an intermediary mechanism to ensure data integrity during parallel operations. The first operation unit reads parity data from memory portions not being accessed by the second operation unit, using this parity information to validate and restore target data, thereby maintaining reliability while enabling high productivity through parallel access.
3Loss of information
If the first operation unit reads from all target memory devices, then complete data is obtained, but access conflicts occur when second operation units are active
Solution Approach 1:
The patent segments the target nonvolatile memory devices into multiple portions and configures the first operation unit to read only from portions not currently accessed by second operation units. This selective reading approach ensures data completeness is maintained through parity data validation while avoiding access conflicts that would reduce operational efficiency.
Solution Approach 2:
The patent transitions from a temporal access model (waiting for memory devices to be free) to a spatial access model (accessing different portions simultaneously). The first operation unit determines which portions of target nonvolatile memory devices are not being accessed by second operation units and reads from those specific portions, maintaining data completeness while eliminating access conflicts.
Data Source
AI summary
A memory system may include a plurality of nonvolatile memory devices, a first operation unit configured to perform a first operation on target data stored in target nonvolatile memory devices, and one or more second operation units configured to perform second operations. The first operation unit performs the first operation by reading target data and parity data from nonvolatile memory devices not associated with second operations concurrently performed by the second operation units.