Memory Parity in Dummy Cell Groups for ECC Latency
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Solution Overview
Problem
Existing memory systems face challenges in implementing error correction coding in units that differ from logical blocks, which are managed by host devices, to enable direct NAND control and reduce latency.
Innovation Solution
A memory system with a memory controller and nonvolatile memory that writes data and parities across multiple planes and dummy memory cell groups, using multidimensional error correction codes and XOR parities to ensure data integrity and allow host device management of data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction coding is performed using logical blocks (multiple physical blocks integrated), then data integrity is improved, but host device cannot directly manage NAND control and latency increases
Solution Approach 1:
The patent segments the error correction coding unit from the logical block structure. Instead of performing ECC on integrated logical blocks, the system performs ECC on individual physical blocks independently. This segmentation allows the host device to manage NAND control at the block level without waiting for logical block assembly, reducing latency while maintaining data integrity through independent block-level error correction.
Solution Approach 2:
The patent introduces a new dimension for error correction by implementing it at the physical block level rather than the logical block level. This dimensional shift in the ECC operation scope enables parallel processing of multiple physical blocks independently, allowing host device to manage control operations without being constrained by logical block integration requirements, thus reducing latency while preserving reliability.
2Ease of operation
If error correction coding is performed on individual physical blocks, then host device can directly manage data access, but error correcting capability across multiple planes is reduced
Solution Approach 1:
The patent implements a nested structure where multiple plane parities are embedded within the overall error correction framework. Each physical block contains parities from multiple planes (P0, P1, P2, P3), and these nested parities work together to provide enhanced error correction capability. This nesting allows the host device to manage individual physical blocks independently while the combined parity information from multiple planes maintains strong error correcting capability across the entire memory system.
Solution Approach 2:
The patent creates a composite error correction structure by combining parities from multiple planes within each physical block. Instead of relying on a single parity structure, the system integrates parity information from P0, P1, P2, and P3 planes into a composite correction mechanism. This composite approach enables the host device to access and manage individual physical blocks directly while the combined multi-plane parity provides robust error correction capability that exceeds what any single plane could offer alone.
Data Source
AI summary
According to one embodiment, a memory system includes a memory controller and a nonvolatile memory with multiple planes each provided with multiple word lines, memory cell groups, dummy word lines, and dummy memory cell groups. The memory controller writes data to a memory cell group connected to a corresponding word line of any of the planes, such that a plane to which k-th data are to be written is different from a plane to which (k+m−1)-th data are to be written, and writes the parities to any of the dummy memory cell groups. The combinations of the data used for generating the different parities are different from each other.