Memory Parity and ECC Pipeline for High-Speed 2-Bit Error Detection
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Solution Overview
Problem
Existing MCU systems face challenges in detecting 2-bit errors during high-speed operation, as current error correcting circuits are complex and not suitable for high-speed pipelines, leading to incorrect error determination and inability to detect 2-bit errors, which is critical for ensuring functional safety in applications like Advanced Driver Assistance Systems.
Innovation Solution
A data processing apparatus with a parity generating circuit that generates parity for multiple bits and a parity/ECC decoder circuit capable of detecting 1-bit or 2-bit errors, allowing for error detection prior to the error correction process, thereby enabling high-speed operation and accurate error detection without stalling the pipeline.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a traditional 1-bit error correction circuit is used, then error correction capability is provided, but the circuit is complex and cannot operate at high speed exceeding 1 GHz
Solution Approach 1:
The patent segments the error detection and correction functions into separate circuits: a simple parity check circuit for high-speed operation and a separate SEC-DED circuit for error correction. This segmentation allows the parity check to operate at high speed (exceeding 1 GHz) while the complex correction function is only activated when errors are detected.
Solution Approach 2:
The patent performs preliminary error detection using a simple parity check before invoking the complex error correction process. The parity check circuit evaluates parity bits in advance to determine whether error correction is needed, enabling high-speed operation for error-free data while preparing the correction mechanism for potential errors.
2Reliability
If only a parity check is performed, then high-speed operation is achieved, but 2-bit errors cannot be detected
Solution Approach 1:
The patent merges the parity check circuit with a SEC-DED (Single Error Correction, Double Error Detection) circuit. The parity check provides high-speed operation while the integrated SEC-DED circuit extends error detection capability to include 2-bit errors, combining the advantages of both approaches.
Solution Approach 2:
The patent creates a multi-functional error handling system where the parity check circuit serves dual purposes: it enables high-speed operation for normal data and triggers the SEC-DED correction mechanism when errors are detected. The system universally handles both error-free and error-containing data through a unified architecture.
3Reliability
If error correction is performed for every read operation, then error correction is ensured, but the pipeline is stalled and high-speed operation is compromised
Solution Approach 1:
The patent performs preliminary error detection using the parity check circuit before initiating error correction. This preliminary action allows the system to identify which data require correction, enabling selective error handling that maintains pipeline throughput for error-free data while correcting only the necessary errors.
Solution Approach 2:
The patent applies partial error correction action by using the simple parity check for most operations (when no errors occur) and reserving the full SEC-DED correction action only for cases where errors are detected. This partial action approach maintains high productivity while ensuring reliability when needed.
Data Source
AI summary
A data processing apparatus includes a memory, a processor which outputs write data when making a write request to the memory, and which inputs read data when making a read request to the memory, a first circuit which is coupled between the memory and the processor, and which includes a parity generating circuit generating a parity comprising a plurality of parity bits from the write data, the parity being written with the write data into the memory, and a second circuit which is coupled between the memory and the processor, and which includes a parity check circuit detecting a presence or an absence of an error of one-bit or two-bits in the read data and the parity read from the memory.