Memory Controller Parity Tables for Segment Error Correction
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Solution Overview
Problem
Current memory systems lack effective mechanisms for detecting and correcting errors in segments stored in memory controllers, which can lead to data integrity issues and reduced reliability.
Innovation Solution
A memory system with a memory controller that includes a calculator for updating and comparing parities to detect errors and a bit inverter to correct them, ensuring accurate data transmission to a memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection and correction mechanisms are added to the memory controller, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by calculating and storing parity bits for each segment before the segment is fully written to the memory controller's storage unit. When a segment is later read, the stored parity can be immediately used to detect and correct errors without requiring complex real-time analysis, thus improving reliability while keeping the overall system relatively simple
Solution Approach 2:
The patent introduces parity bits as an intermediary element that mediates between the stored segment data and the error detection/correction process. These parity bits serve as a simple mathematical checksum that can reveal errors without requiring complex error correction algorithms, thereby improving reliability with minimal increase in device complexity
2Measurement precision
If parity calculation and error correction operations are performed, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent performs parity calculation in advance when segments are written to the storage unit, storing both the segment data and its corresponding parity bits together. This eliminates the need for time-consuming parity recalculation during read operations, as the pre-computed parity can be immediately used for error detection, thus achieving high measurement precision with minimal time loss
Solution Approach 2:
The patent uses a simplified parity bit approach rather than more complex error correction codes. By implementing only the essential parity check functionality (partial action) rather than full-blown error correction algorithms, the system achieves sufficient error detection accuracy while minimizing the processing time required for parity operations
Data Source
AI summary
Disclosed is a memory controller comprising: a memory unit including tables, in which various segments are stored; a calculator configured to update a parity for the segments stored in each of the tables whenever the table is updated when a segment is currently inputted, detect an error in the table based on a previously updated parity and a currently updated parity corresponding to the table; and a bit inverter configured to correct the detected error, and an operating method therefor.