Memory-Specific Parity-Check Coding for Non-Uniform Flash Errors
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Solution Overview
Problem
The use of interleaving in concatenated coding for error control in memory systems is limited by complex circuitry requirements, power consumption, and large die area, which restricts the implementation and efficiency of error correction, especially in flash memory devices where synchronizing independent controllers becomes a challenge.
Innovation Solution
Implementing interleaver-free parallel concatenated encoding and decoding using joint-iterative decoding with independent and parallel encoders that feed forward corrected information, and an error estimation module to select decoders based on error estimates, along with an error tracking module to match bit error probabilities to error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interleaving is used in concatenated coding for error control, then error correction capability is improved, but device complexity and die area increase significantly
Solution Approach 1:
The patent removes the interleaver component from the concatenated coding system, extracting the problematic element that caused complexity and die area issues while maintaining the beneficial error correction capabilities through alternative means
Solution Approach 2:
The patent combines the functions of multiple independent encoders and decoders into a unified parallel concatenated structure without requiring separate interleaving and de-interleaving circuits, thereby reducing overall system complexity
2Reliability
If interleaving is used in concatenated coding, then error distribution is normalized, but power consumption increases
Solution Approach 1:
The patent extracts and removes the interleaver component that consumed excessive power, achieving error distribution management through the natural parallel processing architecture instead
3Quantity of substance
If multi-bit symbol interleaving is used across multiple ports, then storage density is maintained, but synchronization complexity increases
Solution Approach 1:
The patent segments the encoding process into independent parallel encoders that operate autonomously on different data segments, eliminating the need for complex synchronization between ports while maintaining storage density
4Reliability
If interleaving is used, then clustered errors are de-clustered, but the architecture restricts feedback of corrected information
Solution Approach 1:
The patent implements feedback mechanisms that allow corrected information to flow from decoders back to encoders, enabling adaptive error correction that can handle non-uniform error distributions more effectively
Solution Approach 2:
Instead of using interleaving to de-cluster errors, the patent inverts the approach by using parallel independent encoders that naturally process errors in their original positions while maintaining correction capability through feedback loops
Data Source
AI summary
An error control system uses an error control code that corresponds to an error density location profile of a storage medium. The system includes an encoder configured to produce one or more codewords from data using an error control code generator matrix corresponding to the error density location profile of the storage medium. The system also includes a decoder configured to produce decoded data from one or more codewords using an error control code parity-check matrix corresponding to the error density location profile of the storage medium, where columns of the parity-check matrix are associated with corresponding data bits of the storage medium, rows of the parity-check matrix are associated with check bits, and each matrix element of the parity-check matrix having a predefined value indicates a connection between a particular data bit and a particular check bit.