Memory Controller Parity Inversion for ECC Bit Overhead
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Solution Overview
Problem
Existing memory storage devices face challenges in increasing the correction capability for error bits without incurring excessive bit overhead due to the need for more parity bits with stronger error correcting code engines.
Innovation Solution
A memory storage device and data access method that includes a memory controller which verifies data for error bits, determines the quantity of error bits, and decides whether to invert parities of data and flip bits, allowing for increased correction capability by strategically managing parity bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a correction capability of an ECC engine is strengthened (increasing the quantity of correctable error bits), then the correction capability for error bits is improved, but more parity bits are needed which increases bit overhead
Solution Approach 1:
The patent applies dynamics by making the parity bit inversion decision adaptive based on the actual error bit quantity detected during verification. The system dynamically adjusts whether to invert parity bits by comparing the detected error bit count against a threshold, allowing the correction capability to be optimized for the actual error conditions rather than always using maximum correction strength, thereby reducing bit overhead while maintaining reliability.
Solution Approach 2:
The patent changes the parameter of parity bit inversion status based on error bit quantity. By monitoring the number of error bits and conditionally inverting parity bits, the system adjusts the effective correction capability parameter to match the actual error severity, avoiding the need to always allocate maximum parity bits and thus reducing bit overhead while maintaining adequate correction capability.
2Reliability
If more parity bits are allocated to increase correction capability, then the correction capability for error bits is improved, but the data overhead increases
Solution Approach 1:
The system dynamically adjusts the effective use of parity bits by conditionally inverting them based on detected error bit quantity. This dynamic approach allows the system to maintain high correction capability when needed while reducing the effective parity overhead when error conditions are mild, thereby improving reliability without proportionally increasing data overhead.
Solution Approach 2:
The patent changes the operational parameter of parity bits by inverting them conditionally based on error bit count. This parameter change allows the same parity bits to serve different correction functions depending on the error severity, effectively reducing the information overhead required while maintaining the ability to correct errors when they occur.
3Reliability
If verification operation is performed on to-be-written data, then the correction capability for error bits is improved, but the processing time increases
Solution Approach 1:
The patent applies preliminary action by performing verification operations on to-be-written data before it is stored in the memory array. By detecting and recording error bit information in advance, the system can make informed decisions about parity bit inversion and prepare correction strategies beforehand, improving correction capability while managing processing time through proactive error detection rather than reactive correction.
Solution Approach 2:
The system performs self-service by conducting verification operations on its own data before storage. The memory controller autonomously detects error bits, records their information, and decides on parity bit inversion without requiring external intervention, thereby improving correction capability while minimizing additional processing time through integrated self-verification functionality.
Data Source
AI summary
A memory storage device including a memory storage array and a memory controller is provided. The memory storage array is configured to store data. The memory controller is coupled to the memory storage array. The memory controller is configured to write to-be-written data to the memory storage array. The to-be-written data includes a plurality of data bits and a flip bit. The memory controller performs a verification operation on the to-be-written data to determine whether the data bits includes error bits and records information of the error bits. The memory controller, determines, according to a quantity of the error bits, whether to invert parities of the data bits and the flip bit, and records the parity of the flip bit. In addition, a data access method is also provided.