Memory Controller Parity Layout for Faster Logical Page Reads
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Solution Overview
Problem
Existing memory systems face inefficiencies in data reading and writing operations due to uneven distribution of parity clusters across channels, leading to longer read times and reduced performance in logical page operations.
Innovation Solution
The memory system employs a uniform distribution of parity clusters across channels, optimizing the arrangement of parity data to minimize the number of data out command sequences required, thereby improving the efficiency of logical page read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parity clusters are unevenly distributed across channels, then error correction capability is maintained, but read operation time increases and performance decreases
Solution Approach 1:
The patent segments the parity data distribution across multiple channels, dividing the logical page into multiple physical pages that are distributed across different channels. Each channel receives a specific portion of the logical page with appropriately distributed parity clusters, enabling parallel read operations without bottlenecking on any single channel.
Solution Approach 2:
The patent applies local quality by optimizing the distribution of parity clusters specifically for read operations while maintaining error correction capability. By strategically placing parity clusters in specific physical pages on specific channels based on read access patterns and channel capabilities, the system improves read performance in specific locations without compromising overall data integrity.
2Reliability
If more data out command sequences are used, then complete data retrieval is achieved, but operation time increases
Solution Approach 1:
The patent performs preliminary action by pre-organizing the distribution of logical page data across physical pages and channels during the write operation. The controller strategically places data and parity clusters in specific physical pages on specific channels during writing, so that subsequent read operations can retrieve complete data with fewer command sequences by accessing optimally distributed physical pages.
3Productivity
If parity data is concentrated in specific channels, then storage capacity utilization is optimized, but read performance decreases due to channel bottlenecks
Solution Approach 1:
The patent transitions from a single-dimension storage view to a multi-dimensional view by distributing data across channels (first dimension), physical pages (second dimension), and logical pages (third dimension). This multi-dimensional distribution strategy allows the system to optimize storage utilization while avoiding channel bottlenecks by spreading read operations across multiple channels simultaneously.
Data Source
AI summary
According to the embodiment, two or more memory chips each include first storage areas. First memory chips among the two or more memory chips are connected to two or more channels. The memory controller executes a storage operation of storing first data on a group of second storage areas. Each of the second storage area is one of the first storage areas of each of the first memory chips. In the storage operation, the memory controller generates parity data corresponding to first data. The memory controller stores partial parity data that is part of the parity data in the second storage areas of each of the first memory chips. The memory controller stores both the partial parity data and partial first data that is part of the first data, in a second storage area of each of one or more second memory chips.