Memory Parity Layout Using Partial Entries to Cut Buffer Size
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Solution Overview
Problem
Existing memory systems face challenges in efficiently distributing and storing write data entries across multiple memory regions, leading to increased operational complexity, performance degradation, and resource inefficiency, particularly in volatile memory usage.
Innovation Solution
A memory system is designed to distribute write data entries across multiple regions, generating partial parity entries for sub-groups of data, which are stored in non-volatile memory, and performing logical operations to generate parity entries, reducing the need for large buffers and optimizing resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write data entries are distributed across multiple memory regions, then data reliability is improved, but the buffer size required for parity generation increases
Solution Approach 1:
The patent divides write data entries into multiple sub-groups and generates partial parity entries for each sub-group separately. This segmentation allows the system to handle distributed data across multiple memory regions while using smaller, manageable buffer sizes for each partial parity generation operation, rather than requiring a large buffer to hold all data entries simultaneously.
Solution Approach 2:
The patent introduces a hierarchical parity generation approach where partial parity entries are generated for sub-groups first, then combined to form the final parity entry. This two-level structure transforms the problem from a single-dimension large-buffer requirement into a multi-dimensional process with smaller intermediate buffers, effectively reducing the peak memory buffer size needed.
2Reliability
If write data entries are distributed and programmed across multiple regions, then data safety is improved, but operational complexity increases
Solution Approach 1:
The patent segments the parity generation process into multiple independent stages: generating partial parity entries for each sub-group, storing them temporarily, and then combining them to form the final parity entry. This segmentation simplifies each individual operation while maintaining the overall distributed storage safety, making the complex process more manageable and less error-prone.
Solution Approach 2:
The patent performs preliminary generation of partial parity entries for each sub-group before combining them into the final parity entry. This preliminary action allows the system to prepare data in smaller, organized units that can be independently verified and managed, reducing the complexity of the overall parity generation process while ensuring data safety across multiple regions.
3Reliability
If data is distributed across plural regions, then data safety is improved, but the time required for parity generation increases
Solution Approach 1:
The patent employs periodic action by generating partial parity entries for each sub-group in a systematic sequence, storing them temporarily, and then combining them in subsequent periods. This periodic approach allows the system to distribute the parity generation workload over time in manageable cycles, preventing any single operation from becoming a time-consuming bottleneck while maintaining data safety across multiple regions.
Solution Approach 2:
By segmenting the parity generation into independent partial parity operations for each sub-group, the patent enables parallel processing of multiple sub-groups simultaneously. This segmentation transforms a single long-running parity generation operation into multiple shorter, potentially concurrent operations, reducing the total time required while ensuring data safety through distributed storage.
Data Source
AI summary
A memory system includes a memory device and a memory controller. The memory device includes a first memory region for storing plural data entries, a second memory region for storing a parity entry associated with the plural data entries, a third memory region for storing at least one partial parity entry corresponding to at least one sub-group, each sub-group including a part of the plural data entries. The memory controller generates a first partial parity entry corresponding to a first sub-group among the at least one sub-group to store the first partial parity entry in the third memory region, generates a second partial parity entry corresponding to a second sub-group among the at least one sub-group, reads the first partial parity entry from the third memory region, and performs a logical operation on the first partial parity entry and the second partial parity entry to generate the parity entry.