Concurrent Memory Read Write via Parity Bank Segmentation
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Solution Overview
Problem
Conventional memory devices are limited in their ability to perform simultaneous read and write operations, particularly in networking or switching applications, where multiple devices or cores need to access shared memory blocks within the same clock cycle, leading to reduced switching capabilities and increased costs due to the need for synchronized multiple memory systems.
Innovation Solution
A memory device architecture with multiple content memory banks and a parity memory bank allows for concurrent read and write operations by spreading partial write operations over multiple clock cycles, enabling one memory interface to perform read operations independently while another performs partial write operations, using parity information calculated through XOR operations and temporarily stored in registers before being updated in the parity memory bank.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory devices perform a write operation at a particular memory block, then the write operation can be completed, but read operations at the same memory block must be delayed for several clock cycles
Solution Approach 1:
The memory device is divided into multiple independent memory banks (first memory bank, second memory bank, third memory bank) that can operate simultaneously. When a write operation is performed on the first memory bank, read operations can concurrently access the second and third memory banks, thereby eliminating the read delay that would otherwise occur during write operations.
Solution Approach 2:
The patent combines multiple memory banks into a unified memory system with shared control logic and interface. This allows the system to perform both write and read operations simultaneously across different banks, resolving the contradiction between completing writes and avoiding read delays through coordinated parallel operation.
2Adaptability or versatility
If multiple devices or cores need to perform read and write operations in the same memory block during the same clock cycle, then switching capabilities are improved, but conventional memory devices reduce switching capabilities due to access limitations
Solution Approach 1:
The memory system is segmented into multiple independent banks that can be accessed simultaneously by different devices or cores. This segmentation enables multiple read and write operations to occur in parallel during the same clock cycle, thereby improving both adaptability and switching capability without the limitations of conventional single-bank memory.
Solution Approach 2:
The patent transitions from a single-dimension sequential access model to a multi-dimensional parallel access model by introducing multiple memory banks that can be accessed independently. This dimensional expansion allows simultaneous operations from multiple devices or cores, resolving the contradiction between access flexibility and switching performance.
3Speed
If each device is provided with its own respective memory, then access speed is improved, but the direct cost and resources required increase
Solution Approach 1:
The patent merges multiple memory systems into a single shared memory device with multiple banks. This consolidation allows multiple devices or cores to share the same physical memory resources while maintaining the ability to perform simultaneous read and write operations in parallel, thereby achieving high access speed without proportionally increasing memory quantity or cost.
Solution Approach 2:
The shared memory system is designed with universal access capabilities that allow multiple devices or cores to simultaneously access different memory banks. This multi-functionality enables the single memory device to serve multiple purposes and support multiple concurrent operations, achieving the benefits of dedicated memory for each device without requiring separate physical memory for each.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory throughput by allowing multiple locations in content memory banks to be read in a single clock cycle, reduces the delay in servicing read requests during write operations, and maintains system performance without the need for synchronized multiple memory systems, thereby improving switching capabilities and resource efficiency.
Implementation Method 1
generating new parity information for the new content data using the old content data
Data Source
AI summary
A network device includes: a set of content memory banks including a first memory bank; a parity memory bank; a first memory interface; and a second memory interface. The first memory interface is configured to perform a write operation to write new content data to a location in a first content memory bank in a plurality of partial write operations that are spread over two or more clock cycles, including: generating new parity information for the new content data using old content data at the location in the first content memory bank, and storing the new parity information to the parity memory bank. The second memory interface is configured to perform a read operation at the location in the first content memory bank concurrently while the first memory interface is performing at least one of the plurality of partial write operations.