Memory Parity Refresh Using Turbo RAIN for Low Latency
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Solution Overview
Problem
Existing data protection schemes in memory devices increase latency and decrease overall performance, particularly in multi-level cell (MLC) configurations, due to the need for separate write operations for data and parity bits.
Innovation Solution
Perform turbo RAIN operations on memory blocks during idle periods, generating a third set of parity bits from first and second data and parity bits, which are stored for error correction without affecting latency or performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate write operations are performed for data and parity bits in MLC configurations, then error correction capability is improved, but latency increases and overall performance decreases
Solution Approach 1:
The patent combines the write operation of data and parity bits into a single unified operation. Instead of performing separate write operations for data and parity bits as in conventional MLC configurations, the system writes both simultaneously in one operation, thereby reducing latency while maintaining error correction capability through the integrated parity information.
Solution Approach 2:
The system performs preliminary calculations to generate parity bits before the write operation, and prepares the combined data-parity structure in advance. This preliminary preparation allows the actual write operation to complete in a single step, reducing the overall time required while ensuring error correction capability is established beforehand.
2Reliability
If separate write operations are performed for data and parity bits, then data protection is improved, but device complexity increases
Solution Approach 1:
The patent merges the data write and parity write operations into a single combined operation. This reduces the complexity of coordinating multiple separate write operations, managing their timing and synchronization, while still providing comprehensive data protection through the integrated parity mechanism.
3Reliability
If turbo RAIN operations are performed during idle periods, then error correction capability is enhanced, but memory device performance may be affected
Solution Approach 1:
The system performs turbo RAIN operations periodically during idle periods of the memory device. By scheduling these enhanced error correction operations to occur only when the device is not actively processing data requests, the system enhances error correction capability without interfering with normal memory operations and maintaining overall device performance.
Solution Approach 2:
The memory device performs turbo RAIN operations on its own during idle periods without requiring external intervention or sacrificing performance. The system utilizes its own idle capacity to enhance error correction, effectively serving itself without impacting productivity.
Data Source
AI summary
Methods, systems, and devices for storing parity during refresh operations are described. In some examples, refresh operations may be performed on a memory device when the memory device is idle. For example, a refresh operation may entail performing a logical operation on first data and a first set of parity bits and second data and a second set of parity bits. The logical operation may generate a third set of parity bits which may be used for data retention purposes. Moreover, during a read operation, the third set of parity bits may be used to recover corrupt or otherwise invalid data in the event of an error.