Semiconductor Memory Error Correction via Parity Selection
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently correcting errors during self-refresh mode, which can lead to prolonged write and read times, and increased power consumption, especially in portable electronic products.
Innovation Solution
A semiconductor memory device with an error correction function that includes a parity generating circuit, error calculating circuit, and error corrector, capable of adjusting the self-refresh period by generating and selecting parities of different bit lengths based on the partial array self-refresh mode, allowing for reduced power consumption and extended refresh periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction is performed in self-refresh mode using traditional methods, then error correction capability is provided, but power consumption increases and refresh period is limited
Solution Approach 1:
The memory array is divided into multiple banks, and only specific banks are selected for error correction during self-refresh mode based on the PASR signal. This segmentation allows the system to correct errors in only the necessary portions of memory rather than all banks, reducing power consumption while maintaining error correction capability.
Solution Approach 2:
The patent implements partial array self-refresh mode where only a portion of the memory array undergoes error correction during self-refresh. By applying error correction to only the necessary subset of banks rather than the entire array, the system reduces power consumption while still providing adequate error protection for the active memory regions.
2Reliability
If error correction is performed in normal mode, then error correction capability is provided, but write time and read time increase
Solution Approach 1:
Error correction is performed during self-refresh mode, which occurs between normal read/write operations. By completing error correction in advance during the self-refresh period rather than during active data access, the system maintains error correction capability without extending write or read times.
Solution Approach 2:
The system performs error correction periodically during self-refresh cycles rather than continuously during every read/write operation. This periodic execution of error correction during natural refresh intervals eliminates the time penalty from normal mode error correction while maintaining data integrity.
3Speed
If self-refresh period is shortened to improve responsiveness, then system responsiveness improves, but power consumption increases
Solution Approach 1:
By segmenting the memory array into multiple banks and selecting only specific banks for self-refresh error correction based on PASR signals, the system can extend the overall refresh period while still providing timely error correction for active memory regions, thus reducing power consumption without sacrificing responsiveness.
Solution Approach 2:
Different regions of the memory array are treated differently during self-refresh mode. The patent applies error correction selectively to specific banks that require it while allowing other banks to remain in a lower-power state, enabling extended refresh periods with reduced power consumption while maintaining responsiveness for actively used memory regions.
Data Source
AI summary
A semiconductor memory device may include a parity generating circuit, a memory cell array, an error calculating circuit and an error corrector. The parity generating circuit generates parities having different number of bits according to types of a partial array self-refresh mode, and selects one of the parities to output a first parity. The error calculating circuit calculates an error based on a first data corresponding to the input data and a second parity corresponding to the first parity and outputs a first error data. The error corrector corrects the first data based on the first data and the first error data.