Memory Command/Address Parity via Shared Data Pins
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Solution Overview
Problem
In memory systems, performing parity checking on command/address pins is challenging due to constraints on the number of pins available and varying timing requirements, making it impractical to use a dedicated pin for parity, especially when conveying a single bit of CA parity information.
Innovation Solution
The memory device utilizes data-associated pins like DMI, ECC, or RDQS, which are otherwise unused during command cycles, to convey CA parity information, allowing for parity checking without a dedicated pin by generating and inputting or outputting a parity bit concurrently with data operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated pin is used for CA parity checking, then parity checking capability is improved, but the number of available pins is reduced
Solution Approach 1:
The patent applies multi-functionality by enabling data-associated pins (DMI, ECC, RDQS) to serve dual purposes: their primary data transfer function and an additional parity bit transmission function. During command cycles when these pins are unused for data operations, they convey parity information, thus eliminating the need for dedicated parity pins while maintaining comprehensive parity checking capability
2Device complexity
If data-associated pins are used for parity transmission, then pin utilization is optimized, but timing constraints must be precisely met
Solution Approach 1:
The patent implements preliminary action by transmitting the parity bit during the command cycle itself, before the data operation completes. This timing strategy ensures that parity information is available early for validation purposes, and the system is designed to meet the required timing constraints by synchronizing parity transmission with the command cycle timing
Data Source
AI summary
Methods, systems, and devices for targeted command/address parity low lift are described. A memory device may receive a command (e.g., a write command or a read command) from a host device over a first set of pins and may perform data transfer over a second set of pins with the host device during a set of time intervals according to the command. The memory device may exchange a parity bit associated with the command with the host device over a third set of pins during a first time intervals of the set of time intervals. In some cases, the third memory device may exchange at least one additional bit associated with the command with the host device during at least one time interval of the set of time intervals.