Memory Device Parity Data Verification Circuit
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Solution Overview
Problem
The existing memory device test processes are inefficient due to the need to compare input data with output data for each bit, which increases testing time and reduces efficiency, especially when dealing with a large number of memory devices.
Innovation Solution
A memory device with an embedded error detection and correction function that generates and outputs parity data, allowing for verification of data integrity with a smaller set of verification data, thereby reducing the time required for testing and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If input data is compared with output data for each bit in the test process, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent extracts only the essential verification information (parity data) from the complete input and output data sets. Instead of comparing all bits of input data with output data, the system generates and compares only the parity data, which contains the critical error detection information. This extraction principle reduces the verification workload from O(n) bits to O(n/8) bytes, significantly decreasing test time while maintaining measurement precision through the use of cyclic redundancy check (CRC) or parity bit algorithms that preserve error detection capability.
Solution Approach 2:
The patent creates a simplified copy of the verification process by generating parity data as a representative subset of the full data set. Rather than performing complete data comparison, the system uses the parity data copy to infer the integrity of the entire data transfer. This copying approach allows rapid verification of data accuracy without the time cost of bit-by-bit comparison, resolving the contradiction between precision and time loss.
2Measurement precision
If complete input data and output data are transmitted for verification, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts only the necessary verification components (parity data) from the complete data sets, eliminating the need to transmit and process entire input and output data bundles. The extraction of parity data reduces the verification burden to a manageable subset that retains full error detection capability, thereby reducing device complexity in data transmission and processing while preserving measurement precision.
Solution Approach 2:
The patent applies partial action by performing verification on only a portion of the data (the parity data) rather than the complete data sets. This partial verification approach is sufficient to detect errors without requiring the complexity of processing and comparing all bits of input and output data, thus reducing device complexity while maintaining adequate verification accuracy.
3Measurement precision
If verification data of the same size as input data is output, then measurement precision is improved, but productivity decreases
Solution Approach 1:
The patent extracts verification information into a compact parity data format that is significantly smaller than the original input data (typically 1/8th the size). This extraction enables rapid verification processing and faster output transmission, directly improving test process efficiency and productivity while maintaining the ability to detect data integrity errors through the preserved parity information.
Solution Approach 2:
The patent changes the parameter of verification data size from equal to input data size to a reduced size (parity data). This parameter change optimizes the balance between verification precision and processing speed, allowing the system to maintain error detection capability while significantly reducing the time required for verification and improving overall test productivity.
Data Source
AI summary
A memory device includes memory banks that each include a bank array having memory cells, a row decoder, and a column decoder. Each memory cell includes a capacitor and a transistor, a write circuit to store input data received at the memory device from a test device in the bank array, a read circuit to generate output data based on reading data stored in the bank array, a parity data management circuit to generate first parity data smaller than the input data using the input data, generate second parity data smaller than the output data using the output data, and generate third parity data using the first and second parity data, and an output circuit to output at least one of the first, second, and third parity data as verification data, in response to receipt of a request from the test device at the memory device.