Memory Device Parity Bit Wear Distribution

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Solution Overview

Problem

Existing ECC-enabled memory devices face endurance issues due to repeated writing of parity bits during partial-write cycles, which disadvantageously impacts the longevity of memory cells.

Innovation Solution

A control logic circuit dynamically changes the cells presenting parity bits during each partial-write cycle by swapping data and parity bits, allowing updated parity bits to be written to cells originally storing data and vice versa, thereby distributing the write load more evenly across cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If partial-write cycles are performed to update subsets of data bits, then data update efficiency is improved, but the endurance of memory cells storing parity bits deteriorates due to repeated writing

Engineering Contradiction:
Improvedata update efficiencyVSAvoidmemory cell endurance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies dynamics by making the mapping between parity bit groups and memory cells variable rather than fixed. The control logic circuit dynamically adjusts which cells store which parity bit groups based on the current partial-write cycle, allowing the system to adapt to different update patterns and distribute write operations evenly across cells, thereby maintaining high data update efficiency while preserving memory cell endurance

Inventive Principle:
Principle #15Dynamics

2Reliability

If parity bits are repeatedly written to the same cells during multiple partial-write cycles, then error correction functionality is maintained, but the longevity of memory cells deteriorates

Engineering Contradiction:
Improveerror correction functionalityVSAvoidmemory cell longevity
Core Design Contradiction:
ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent implements periodic action by systematically cycling through different cell assignments for parity bit groups across multiple partial-write cycles. Instead of permanently assigning specific cells to specific parity bit groups, the system periodically reassigns them in a controlled manner, ensuring that each cell undergoes write operations at uniform intervals. This periodic reassignment maintains error correction functionality while preventing any single cell from experiencing concentrated wear, thereby extending memory cell longevity

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS11556414B2Memory device
Publication Date: 2023.01.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11556414B2 patent drawing
  • US11556414B2 patent drawing
  • US11556414B2 patent drawing

AI summary

A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N−1 groups and the plurality of parity bits form a first group different from the N−1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N−1 groups; and providing a second word comprising updated data bits that form a second one of the N−1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N−1 groups.