Distributed Memory Parity Layout for Wider ECC Word Access
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Solution Overview
Problem
Existing memory systems require a large number of parity bits to ensure reliable error correction, which increases memory capacity and power consumption, and existing methods for distributing parity bits across multiple words often result in performance drops during read access.
Innovation Solution
A method that distributes parity bits across multiple data words, allowing for error detection and correction within a group of words, using a combination of word parity information and shared parity bits, enabling efficient error correction without significant performance impact on read access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity bits are added to each data word for error correction, then error detection and correction reliability is improved, but memory capacity and power consumption increase
Solution Approach 1:
The patent divides the error correction functionality into two segments: word-level parity bits stored with each data word for single-word error correction, and group-level distributed parity bits shared across multiple words for multi-word error correction. This segmentation allows the system to handle common single-word errors efficiently while providing comprehensive multi-word error correction only when needed, reducing the total parity bit overhead compared to providing full error correction capability for every word individually.
Solution Approach 2:
The distributed parity bits serve multiple functions: they can be used for error detection in single words, error correction in single words, and error detection/correction across groups of words. By making the parity bits multi-functional, the system achieves comprehensive error protection without requiring separate dedicated parity bits for each error correction scenario, thereby reducing overall memory capacity requirements.
2Quantity of substance
If distributed parity bits are shared across multiple data words, then memory capacity efficiency is improved, but read access performance deteriorates
Solution Approach 1:
The patent segments error correction into two hierarchical levels: word-level correction using locally stored parity bits that can be accessed immediately with the data word, and group-level correction using distributed parity bits that are only accessed when word-level correction is insufficient. This segmentation ensures that common read operations experience no performance penalty, while rare multi-word error cases can utilize the distributed parity bits.
Solution Approach 2:
The system performs preliminary error correction at the word level using locally stored parity bits before attempting to use distributed parity bits. This preliminary action handles the majority of error cases without requiring access to distributed parity bits, thereby maintaining fast read access performance for common scenarios while preserving the capability to handle rare multi-word errors.
3Reliability
If more parity bits are stored with each data word, then error correction capability is improved, but power consumption increases
Solution Approach 1:
The patent segments the error correction burden by distributing parity bits across groups of words rather than concentrating them with each individual word. This allows the system to achieve comprehensive error correction capability across multiple words while reducing the power consumption associated with reading and processing large numbers of parity bits for each individual word access.
Solution Approach 2:
The system implements partial error correction at the word level using minimal locally stored parity bits, and only activates the full distributed parity bit system when necessary for multi-word errors. This partial action approach provides adequate error protection for common cases with minimal power consumption, while maintaining the capability to handle rare severe error conditions.
Data Source
AI summary
Various embodiments relate to a method for storing and reading data from a memory. Data words stored in the memory may be grouped, and word specific parity information and shared parity information is generated, and the shared parity information is distributed among the group of words. During reading of a word, if more errors are detected than can be corrected with word parity data, the shared parity data is retrieved and used to make the error corrections.