In-Memory Partial ECC Decoding for Lower-Power Memory Reads
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Solution Overview
Problem
Current memory systems suffer from high energy consumption and area overhead due to redundant ECC bit operations and parallel accesses, leading to frequency limitations and long cycle times in modern designs.
Innovation Solution
Incorporating ECC logic within the memory circuitry to perform partial decoding of ECC results, reducing the need to read out all data and ECC bits, and implementing a two-phase tag way-halting architecture to minimize unnecessary memory accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all data and ECC bits are read out from memory for full ECC decoding, then accurate error detection and correction is achieved, but power consumption increases and operation speed decreases
Solution Approach 1:
The patent divides the ECC decoding process into two segments: (1) partial syndrome calculation performed within the memory array using distributed logic that processes only relevant portions of data and ECC bits, and (2) complete decoding performed outside the memory. This segmentation allows error detection to begin in-memory without requiring full data readout, reducing power consumption while maintaining detection accuracy for errors occurring within the processed segments.
Solution Approach 2:
The patent implements partial ECC decoding by calculating only the necessary syndrome bits required to detect errors in the specific data portion being accessed. Instead of performing complete decoding on all data and ECC bits, the system performs partial syndrome calculation on selected columns, which is sufficient to detect errors in the accessed data without the overhead of processing the entire memory block.
2Reliability
If all data and ECC bits are read out from memory for full ECC decoding, then accurate error detection and correction is achieved, but operation speed decreases due to longer cycle times
Solution Approach 1:
The ECC decoding is segmented into in-memory partial syndrome calculation and out-of-memory complete decoding. The partial syndrome calculation is performed concurrently with data readout using distributed logic within the memory array, overlapping computation with data transfer. This eliminates the sequential dependency where complete decoding must wait for full data readout, thereby reducing cycle time while maintaining decoding accuracy.
Solution Approach 2:
The patent performs preliminary syndrome calculation within the memory array before the data is fully read out to the external decoder. This preliminary computation prepares partial error detection results in advance, allowing the external decoder to receive pre-processed information that reduces its computation time. The preliminary action of in-memory syndrome calculation begins before data readout completes, overlapping operations to reduce total cycle time.
3Reliability
If redundant ECC logic is implemented throughout the memory system, then error correction capability is improved, but area overhead increases
Solution Approach 1:
The patent implements ECC logic with local quality by distributing minimal syndrome calculation logic within specific memory columns or blocks that correspond to accessed data, rather than uniformly throughout the entire memory array. This localized approach places computation resources only where needed for the accessed data portions, reducing overall area overhead while maintaining error correction capability for accessed regions. The in-memory logic processes only the relevant data columns, avoiding the need for redundant logic across the entire memory system.
Data Source
AI summary
A memory circuitry with optimized error correction code architecture includes a memory array; a wordline driver, the wordline driver coupled to receive an address and select a corresponding wordline of the memory array; read circuitry coupled to bitlines of the memory array; and error correction code (ECC) logic coupled to receive outputs of a set of columns selected by the read circuitry. The ECC logic performs a partial decoding of the outputs to output a partial ECC result that represents if there is an error and where that error is located.