Memory Device Partial Pages Segmentation
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Solution Overview
Problem
The challenge lies in increasing the net die in semiconductor memory devices without incurring significant investment costs or complexity, as scaling down line widths becomes increasingly difficult due to miniaturization limitations and large wafer implementation is costly and time-consuming.
Innovation Solution
The proposed solution involves a memory device architecture with a cell region divided into multiple memory blocks and sub-blocks, each coupled to bit lines and word lines, utilizing a pass transistor circuit and block switch circuit to efficiently manage data transfer and voltage distribution, allowing for a more compact and balanced layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the diameter of wafer is increased to increase net die, then productivity and price competitiveness are improved, but investment cost and equipment development complexity increase significantly
Solution Approach 1:
The patent divides a single large wafer into multiple smaller wafers, each containing a portion of the memory device. This segmentation allows standard-sized wafers to be used while achieving the equivalent net die of a larger wafer, avoiding the need for expensive large-wafer equipment while maintaining productivity.
2Productivity
If line width is scaled down to reduce chip size and increase net die, then chip size is reduced and net die is increased, but miniaturization technology limitations make it increasingly difficult
Solution Approach 1:
Instead of continuing to scale down line widths in the lateral dimension, the patent transitions to the vertical dimension by stacking multiple wafers and using three-dimensional transistor structures. This dimensional transition allows net die increase without further lateral miniaturization, avoiding the precision limitations of continued scaling.
3Quantity of substance
If memory block size is increased to improve storage capacity, then storage capacity is improved, but access time and power consumption increase
Solution Approach 1:
Each memory block is divided into multiple sub-blocks that can be independently accessed. This segmentation allows the memory system to access only the specific sub-block containing the desired data, reducing access time and power consumption while maintaining large storage capacity through the aggregation of multiple sub-blocks.
Data Source
AI summary
A memory device includes a plurality of bit lines extending in a first direction and arranged in a second direction; and a cell region including a plane which is coupled to the plurality of bit lines, wherein the plane is divided into a plurality of memory groups each including a plurality of partial pages to be disposed in a plurality of rows in the first direction.