Memory Cell Reading via Partial Readings and Soft Information

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Solution Overview

Problem

Conventional NAND memory cell arrangements face challenges in increasing memory density and reducing costs per bit while efficiently obtaining multiple bits of information from memory cell states without increasing complexity, particularly in distinguishing between multiple threshold voltage levels.

Innovation Solution

The approach involves providing a memory cell arrangement that can program and read multiple threshold voltage levels, using soft information by performing multiple single-level read operations with different voltage reference levels, and employing an iterative process with sliding threshold values to achieve finer granularity in voltage interval classification, allowing for improved threshold estimation and error correction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple bits of information are obtained from memory cell states through soft information reading, then memory density and information retrieval capability are improved, but device complexity increases due to additional read operations and processing requirements

Engineering Contradiction:
Improvememory densityVSAvoidreading operation complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent segments the reading process into multiple partial readings with different reference voltage levels. Instead of performing a single complex read operation to obtain multiple bits, the system performs several simpler read operations with different voltage references (e.g., first reference voltage, second reference voltage, third reference voltage) and combines the results to obtain soft information. This segmentation reduces the complexity of individual operations while achieving the goal of retrieving multiple bits of information.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs dynamic adjustment of reference voltage levels during the reading process. The controller dynamically selects different reference voltages for different read operations based on the memory cell states being read. This dynamic approach allows the system to adaptively retrieve information at different precision levels without requiring a fixed complex reading mechanism, thereby reducing overall system complexity while maintaining high memory density capabilities.

Inventive Principle:
Principle #15Dynamics

2Measurement precision

If multiple threshold voltage levels are distinguished through additional read operations, then measurement precision is improved, but reading time and processing duration increase

Engineering Contradiction:
Improvethreshold voltage distinction precisionVSAvoidreading operation time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs preliminary read operations with different reference voltages to classify memory cell states into different regions before final decision-making. By conducting these preliminary readings in parallel or in a structured sequence, the system pre-divides the threshold voltage ranges into multiple regions (e.g., first region, second region, third region) which facilitates faster subsequent processing and reduces the time required for precise threshold distinction.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent employs periodic reading operations where the controller repeatedly reads memory cell states using different reference voltage levels in a systematic sequence. This periodic action allows the system to accumulate sufficient information about threshold voltage distributions without requiring continuous complex operations. The periodic nature of the readings enables efficient time management while achieving high measurement precision through multiple sampled measurements at different voltage levels.

Inventive Principle:
Principle #19Periodic action

3Ease of operation

If hard decision reading is used to convert threshold voltage to digital values, then ease of operation is improved, but information loss occurs due to inability to recover intrinsic gain loss or distribution shift

Engineering Contradiction:
Improvedigital value conversion simplicityVSAvoidmemory cell intrinsic information
Core Design Contradiction:
Ease of operationVSLoss of information

Solution Approach 1:

The patent introduces soft information as an intermediary representation between the raw memory cell states and final digital decisions. Instead of directly converting threshold voltage to digital values through hard decision, the system first obtains soft information that preserves additional bits about the memory cell state distribution. This soft information acts as an intermediary that maintains intrinsic gain loss and distribution shift characteristics, allowing for more accurate error correction while still enabling straightforward digital conversion when needed.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements feedback mechanisms where the controller analyzes the results of multiple partial readings and adjusts subsequent operations accordingly. By feedback from the soft information obtained during reading, the system can identify patterns in memory cell intrinsic characteristics and use this information to improve error correction codes and digital signal processing. This feedback loop preserves valuable information about memory cell states that would otherwise be lost in hard decision conversion, while maintaining operational simplicity through automated adaptive processing.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS7800943B2Integrated circuit having a memory cell arrangement and method for reading a memory cell state using a plurality of partial readings
Publication Date: 2010.09.21 SAMSUNG ELECTRONICS CO LTD
  • US7800943B2 patent drawing
  • US7800943B2 patent drawing
  • US7800943B2 patent drawing

AI summary

Embodiments of the invention relate generally to an integrated circuit having a memory cell arrangement and a method for reading a memory cell state using a plurality of partial readings. In an embodiment of the invention, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include at least one memory cell, the memory cell being capable of storing a plurality of memory cell states being distinguishable by a predefined number of memory cell threshold values, and a controller configured to read a memory cell state of the at least one memory cell using a number of reference levels that is higher than the predefined number of memory cell threshold values, wherein the reading includes a first partial reading using a first set of a plurality of reference levels and a second partial reading using a second set of a plurality of reference levels, wherein the second set of a plurality of reference levels includes at least one reference level which is different from the reference levels of the first set of a plurality of reference levels.