Semiconductor Memory Partial Self Refresh Skip Address Control
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Solution Overview
Problem
Existing semiconductor memory devices require periodic refresh operations to prevent data loss due to charge leakage, but they lack the ability to exclude specific memory regions from self-refresh operations, leading to inefficiencies and potential data loss in regions that do not require refresh.
Innovation Solution
A semiconductor memory device and system that includes a memory circuit, a skip address storage unit, a refresh address generator, and an address comparator, which allow for the exclusion of specific memory regions from self-refresh operations by storing skip addresses and generating refresh addresses, enabling targeted refresh control signals to be provided to the memory circuit based on comparisons.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If self refresh is performed for all memory regions, then data integrity is maintained, but power consumption increases unnecessarily in regions that do not require refresh
Solution Approach 1:
The memory array is divided into multiple banks, and each bank can be independently controlled for refresh operations. The patent implements partial self-refresh by enabling refresh for specific banks that contain valid data while disabling it for banks that do not require refresh, thus segmenting the refresh control at the bank level to reduce unnecessary power consumption.
Solution Approach 2:
Different refresh control strategies are applied to different memory banks based on their specific requirements. The patent uses bank-specific refresh control signals to apply local quality - full refresh for banks with valid data and no refresh for banks without valid data, optimizing power consumption while maintaining data integrity where needed.
2Reliability
If self refresh is performed for all memory regions, then data loss is prevented, but operational efficiency decreases due to unnecessary refresh cycles
Solution Approach 1:
Instead of performing complete refresh cycles on all memory banks, the patent applies partial refresh action only to the specific banks that require it. The refresh control logic determines which banks need refresh and applies refresh cycles only to those banks, avoiding excessive refresh operations on banks that do not require it, thus improving operational efficiency.
Solution Approach 2:
The refresh operation is segmented at the bank level, allowing independent control of refresh for each bank. This segmentation enables the system to perform refresh only on necessary banks, improving productivity by reducing the total number of refresh cycles while still preventing data loss in banks that require it.
3Device complexity
If refresh control is applied uniformly to all banks, then implementation is simple, but adaptability to different refresh requirements of different banks is reduced
Solution Approach 1:
The refresh control system is made dynamic by introducing bank-specific valid data indicators and conditional refresh control logic. The refresh control signals are dynamically adjusted based on the validity status of each bank, allowing the system to adapt to different refresh requirements of different banks while maintaining a relatively simple implementation through systematic control logic.
Solution Approach 2:
The refresh control logic is designed with multi-functionality to handle both full refresh and partial refresh scenarios. The same control structure can adapt to different bank requirements by evaluating the valid data indicators, providing universality in handling various refresh situations without requiring completely separate control paths for each case.
Data Source
AI summary
A semiconductor memory device capable of performing a partial self refresh and semiconductor memory system including same is provided. The semiconductor memory device includes: a memory circuit including a memory array; a skip address storage unit storing an address of an excluded region not requiring refresh in the memory array as a skip address; a refresh address generator providing an address of a region of the memory array requiring refresh as a refresh address; and an address comparator receiving and comparing the skip address and refresh address, and providing a refresh control signal to the memory circuit based on the comparison.