Memory Partitioning for Multi-Core Avionics Execution Speed
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Solution Overview
Problem
Non-optimal combinations of cores and memory pools in multi-core processor systems can lead to slowed application execution times, resulting in suboptimal performance in avionics systems.
Innovation Solution
A method is provided to determine efficient memory partitioning by receiving input data, defining active core combinations and corresponding memory pool subsets, performing uncached transactions, measuring execution times, and identifying combinations with improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If non-optimal combinations of cores and memory pools are used, then device complexity is reduced, but application execution speed deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-determining optimal core-memory pool combinations through systematic evaluation of all possible configurations. The system performs comprehensive testing and characterization before actual application execution, storing the results for rapid retrieval during runtime, thus avoiding the need to evaluate all combinations during actual operation.
Solution Approach 2:
The patent utilizes parameter changes by systematically varying core assignments and memory pool configurations to identify optimal combinations. The system evaluates multiple parameter sets including different core counts, memory pool sizes, and allocation patterns to determine the configuration that maximizes application execution speed for specific workloads.
2Speed
If optimal combinations of cores and memory pools are identified through comprehensive testing, then application execution speed is improved, but loss of time increases due to extensive performance evaluation
Solution Approach 1:
The patent resolves this contradiction by performing the time-consuming performance evaluation in advance, before the application actually needs to execute. The optimal configurations are determined through comprehensive testing during system initialization or configuration phase, and then stored for rapid deployment, eliminating the time penalty during actual application runtime.
Solution Approach 2:
The patent applies copying by creating a model or representation of the optimal core-memory pool configurations through systematic evaluation. Once the optimal configuration is identified through extensive testing, this configuration model is stored and reused for multiple applications with similar characteristics, avoiding the need to repeat the entire evaluation process.
3Manufacturing precision
If comprehensive performance testing is conducted for all core and memory pool combinations, then manufacturing precision of performance optimization is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by breaking down the comprehensive evaluation process into manageable components: individual core performance characterization, memory pool performance evaluation, and combined configuration assessment. This segmented approach allows systematic testing of each element separately before evaluating their interactions, making the overall process more tractable and less complex.
Solution Approach 2:
The patent utilizes parameter changes by systematically varying specific parameters such as core count, memory pool size, and allocation patterns in a controlled manner. By changing one parameter at a time while holding others constant, the system can precisely measure the impact of each parameter on performance, achieving high optimization precision without requiring exhaustive testing of all possible combinations simultaneously.
Data Source
AI summary
A method comprises: receiving input data comprising a number of read and write uncached transactions, a transaction density, a number of active cores (N active cores) of the at least two cores, main memory address layout, and number of and an identifier for each of: banks and ranks in main memory, interconnects, cache pools, and memory controllers; defining all sets of active cores; defining up to N sets of memory pools; performing, for combinations of at least one set of active cores with each of at least one subset, the specified number of read and write uncached transactions with main memory at a specified transaction density for each defined combination of each active core combination and each defined memory pools; measuring the execution time of such performance for each combination; storing the execution time for each combination; and identifying at least one combination having a lower execution time.