Memory Partitioning for I-R Voltage Drop Detection in BIST
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Solution Overview
Problem
Integrated circuits with embedded memories face defects due to I-R voltage drops during full operation, which are not detected by conventional built-in self test (BIST) methods as the remainder of the SOC circuit is shut down during testing, leading to potential functional failures when the circuit is active.
Innovation Solution
The method involves partitioning the memory into sections, allowing components to access one part while executing BIST on another part, simulating partial or full SOC operation to introduce a controlled I-R voltage drop and detect faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional BIST is executed with the SOC circuit shut down, then test execution is simple and fast, but I-R voltage drop defects are not detected
Solution Approach 1:
The memory is divided into multiple partitions, allowing the BIST to execute on one partition while other partitions remain accessible to SOC components. This segmentation enables the test to run with the SOC circuit active, thereby detecting I-R voltage drop defects that would be invisible in a fully shut-down environment.
Solution Approach 2:
The memory system is designed to serve dual purposes: it functions as both the test target and the operational memory for SOC components simultaneously. By allowing concurrent access from both BIST and SOC components, the system achieves multi-functionality that enables defect detection under realistic operating conditions.
2Reliability
If the entire SOC circuit is activated during BIST, then I-R voltage drop defects can be detected, but memory access conflicts occur between BIST and SOC components
Solution Approach 1:
The memory is divided into multiple partitions, allowing the BIST to execute on one partition while other partitions remain accessible to SOC components. This segmentation enables the test to run with the SOC circuit active, thereby detecting I-R voltage drop defects that would be invisible in a fully shut-down environment.
Solution Approach 2:
Different partitions of the memory have different access permissions: one partition is dedicated to BIST execution while other partitions are reserved for SOC component access. This local differentiation of access rights eliminates conflicts by ensuring that BIST and SOC components operate on separate memory regions.
3Ease of manufacture
If the memory is tested without SOC components active, then current draw is low and testing is straightforward, but the test does not reflect real operating conditions
Solution Approach 1:
The memory system is designed to serve dual purposes: it functions as both the test target and the operational memory for SOC components simultaneously. By allowing concurrent access from both BIST and SOC components, the system achieves multi-functionality that enables defect detection under realistic operating conditions.
Solution Approach 2:
The test system dynamically adapts to real operating conditions by allowing SOC components to remain active during BIST execution. This dynamic approach ensures that the test reflects actual voltage drops and current conditions that occur during normal operation, improving measurement precision.
Data Source
AI summary
A built-in self test (BIST) method and system for testing a memory included on an integrated circuit includes activating a component of the integrated circuit, partitioning the memory into a first part for use by non-BIST components and second part for BIST, and executing BIST on the second part of the memory while the component is operating. While the BIST is executing, the non-BIST components can access the first part of the memory and perform normal functional operations. The BIST method and system finds memory faults that are related to an I-R voltage drop due to the physical placement of the memory relative to power supply sources.