Memory Partitioning for Concurrent Read Write Operations

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Solution Overview

Problem

In memory devices with shared electronic circuitry among partitions, pending write operations can hinder read operations, leading to slower read times and reduced performance.

Innovation Solution

A microcontroller within the memory device interrupts write operations in the same partition when a read command is received, allowing concurrent read operations by determining the partition through most-significant bits of the address and resuming the write operation after the read is complete.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a pending write operation is occurring in one portion of a group of memory cells, then the write operation can proceed without interruption, but a read operation cannot occur in another portion of the same group, resulting in slower read operations

Engineering Contradiction:
Improvewrite operation completenessVSAvoidread operation speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The memory array is divided into multiple independent partitions, each with its own dedicated electronic circuitry (sense amplifiers, row/column decoders). This segmentation allows read and write operations to occur simultaneously in different partitions without interfering with each other, resolving the contradiction between write operation completeness and read operation speed.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If memory cells within a group share common electronic circuitry, then device complexity is reduced, but read operations are blocked when write operations are pending, reducing overall performance

Engineering Contradiction:
Improveelectronic circuitry sharingVSAvoidoverall memory performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

Instead of sharing common electronic circuitry across all memory cells, the patent segments the memory into multiple partitions with dedicated circuitry for each partition. This increases hardware resources but eliminates the performance bottleneck caused by circuitry contention, thereby improving overall memory productivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of parallelism by creating multiple independent memory partitions that can operate simultaneously. This dimensional expansion from sequential shared-resource operation to parallel dedicated-resource operation resolves the performance limitation while maintaining reasonable device complexity through systematic replication.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10248592B2Interrupted write operation in a serial interface memory with a portion of a memory address
Publication Date: 2019.04.02 MICRON TECHNOLOGY INC
  • US10248592B2 patent drawing
  • US10248592B2 patent drawing
  • US10248592B2 patent drawing

AI summary

Subject matter disclosed herein relates to read and write processes of a memory device.