Nonvolatile Memory Pass/Fail Check Circuit
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Solution Overview
Problem
Nonvolatile memory devices face reliability issues due to disconnected or high-resistance vias during the manufacturing process of stacked memory cells, leading to inconsistent program speeds and potential program failures.
Innovation Solution
A nonvolatile memory device is designed with a memory cell array, row decoder circuit, page buffer circuit, and pass/fail check circuit, which detects program speeds across different bitline groups to determine program failures based on threshold differences, preventing data write to faulty cells and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If vias are manufactured during the fabrication process of stacked memory cells, then memory cells can be connected through wordlines, but some vias may become disconnected or have higher than intended resistance leading to program failures
Solution Approach 1:
The patent applies preliminary action by performing a test program operation before normal data programming to detect potential via defects. The test operation identifies memory cells with abnormal program speeds caused by disconnected or high-resistance vias, allowing these faulty cells to be marked and excluded from subsequent data programming, thereby preventing data loss while maintaining the standard via manufacturing process
Solution Approach 2:
The memory device performs self-diagnosis through the test program operation, automatically detecting its own defective cells without external intervention. The pass/fail check circuit evaluates program speeds and identifies faulty cells, enabling the device to self-correct by preventing data programming to these cells, thus improving reliability without adding external testing equipment
2Reliability
If program speed detection is implemented across all memory cells, then program failures can be detected, but the device complexity increases due to additional circuits and operations
Solution Approach 1:
The patent segments the memory cell array into multiple bitline groups, with each group independently evaluated by the pass/fail check circuit. This segmentation allows parallel detection of program speeds in different regions, improving detection coverage while distributing the circuit complexity across multiple simpler units rather than requiring a single complex centralized detection system
Solution Approach 2:
The pass/fail check circuit performs multiple functions: it detects program speeds, compares them against reference values, identifies faulty cells, and generates pass/fail signals. By consolidating these functions into a single multi-functional circuit rather than separate dedicated circuits for each function, the patent reduces overall device complexity while maintaining comprehensive program failure detection capability
Data Source
AI summary
Disclosed is a nonvolatile memory device which includes a memory cell array, a row decoder circuit that selects one wordline as a target of a program operation, a page buffer circuit that stores data to be written in memory cells connected with the selected wordline in the program operation, and a pass/fail check circuit that determines a pass or a fail of the program operation. In the program operation, the pass/fail check circuit detects a first program speed of first memory cells and a second program speed of second memory cells, and determines a program fail based on the first program speed and the second program speed.