3D Memory Pass Gate Layout for Smaller Peripheral Circuit Area
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Solution Overview
Problem
The increasing number of stacked conductive layers in three-dimensional semiconductor memory devices leads to an increased area occupied by peripheral circuit structures, which hinders the integration of memory cells.
Innovation Solution
The semiconductor memory device incorporates a unique structure with cell pillar structures, word line stack structures, and pass gates arranged in specific orientations and spacings, along with insulative pillar structures, to minimize the area occupied by peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the stacked number of conductive layers is increased to improve memory cell integration, then the memory storage capacity is improved, but the area occupied by peripheral circuit structures is increased
Solution Approach 1:
The patent transitions from two-dimensional planar arrangement to three-dimensional vertical stacking of conductive layers and memory cells. Multiple word lines, bit lines, and memory cells are stacked in the vertical direction, enabling high-density integration without increasing the horizontal footprint of peripheral circuits.
Solution Approach 2:
The patent implements nested structures where conductive layers are stacked within a confined vertical space. Word lines, bit lines, and memory cell structures are nested multiple times in the vertical direction, achieving high integration density while maintaining a compact overall structure that minimizes peripheral circuit area.
2Quantity of substance
If the stacked number of conductive layers is increased to improve memory cell integration, then the memory storage capacity is improved, but the device complexity is increased
Solution Approach 1:
The patent divides the stacked structure into distinct functional segments: word line stacks, bit line stacks, memory cell regions, and peripheral circuit regions. Each segment is independently structured and controlled, simplifying the overall device complexity despite the high number of stacked layers by providing modular organization.
Solution Approach 2:
The patent applies different structural configurations to different regions of the device. Memory cell regions utilize high-density vertical stacking, while peripheral circuit regions employ optimized layouts suitable for control functions. This localized optimization reduces overall device complexity by matching structure to function in each region.
Data Source
AI summary
A semiconductor memory device includes a plurality of conductive layers arranged in a vertical direction, a plurality of active layers connected to the plurality of conductive layers, a plurality of pass gates each penetrating the plurality of active layers, and a plurality pass gate insulating layers surrounding sidewalls of the plurality of pass gates, respectively.