3D Memory Word Line Loading via Segmented Pass Transistors
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Solution Overview
Problem
Three-dimensional (3D) nonvolatile memory devices face challenges in maintaining operational reliability due to variations in word line loading across memory cells, which affect data storage and retrieval efficiency.
Innovation Solution
The semiconductor memory device incorporates a stacked body with first and second pass transistors that couple global word lines to local lines, featuring a stepped structure and block select lines to evenly distribute operating voltages across memory cells, minimizing differences in word line loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are vertically stacked in 3D structure to increase integration density, then storage capacity is improved, but variations in word line loading increase causing operational reliability degradation
Solution Approach 1:
The memory block is divided into multiple memory regions (first memory region and second memory region) with different numbers of memory strings. This segmentation allows different word line loading characteristics in different regions, compensating for the variations caused by 3D vertical stacking and achieving more uniform overall loading distribution.
Solution Approach 2:
Different memory regions are designed with different numbers of memory strings to create local variations in structure. The first memory region has a first number of memory strings while the second memory region has a second number of memory strings, creating local quality differences that balance the word line loading across the entire 3D stacked structure.
2Reliability
If pass transistors are added to couple global word lines to local lines, then word line loading distribution is improved, but device complexity increases
Solution Approach 1:
The pass transistors are configured to serve multiple functions: they act as switching elements to connect global word lines to local lines, provide loading distribution across memory cells, and enable selective activation of different memory regions. This multi-functionality reduces the need for additional dedicated components, thereby limiting the increase in device complexity.
Data Source
AI summary
Provided herein is a semiconductor memory device. The semiconductor memory device includes a stacked body, and first pass transistors and second pass transistors configured to couple global word lines to local lines, wherein any one of the plurality of conductive lines is a block select line, and gates of the first pass transistors and the second pass transistors are coupled to the block select line.