Memory Device Pass-Transistor Circuit for Word-Line Timing
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Solution Overview
Problem
The increasing complexity and size of memory devices due to the need for high integration density leads to challenges in reducing the overall chip size and minimizing loading time skew for word lines, as the number of pass transistors connected to vertically stacked word lines increases.
Innovation Solution
A memory device design with a pass transistor circuit that includes an odd number of pass transistor groups, where transistors connected to word lines at the same level are adjacently disposed, reducing wiring resistance and loading time skew, and a COP structure where the pass transistor circuit is disposed under a stair-stepped area, maintaining chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of pass transistors connected to vertically stacked word lines is increased to increase integration density, then the integration density is improved, but the overall chip size increases
Solution Approach 1:
The pass transistor circuit is arranged in a stair-stepped configuration that extends in both horizontal and vertical dimensions. By utilizing the vertical dimension through stacked word lines and the horizontal dimension through adjacently disposed pass transistors, the design achieves high integration density without proportionally increasing the overall chip area. The odd number of pass transistor groups creates a compact footprint by efficiently utilizing space in multiple dimensions.
2Quantity of substance
If the number of pass transistors connected to vertically stacked word lines is increased, then the integration density is improved, but the loading time skew for word lines increases
Solution Approach 1:
The pass transistor circuit employs an asymmetric arrangement where an odd number of pass transistor groups are adjacently disposed. This asymmetric configuration, with pass transistors positioned at different locations relative to the word lines, creates balanced signal paths that reduce loading time skew. The asymmetric design allows for optimized signal distribution across the word lines, compensating for the increased number of pass transistors.
Solution Approach 2:
The pass transistors are adjacently disposed in specific local regions to create optimized signal paths. By strategically positioning pass transistors in different local areas with different configurations, the design achieves uniform signal distribution and minimizes loading time skew across all word lines, while maintaining high integration density through the overall arrangement.
3Loss of time
If pass transistors are adjacently disposed to reduce wiring resistance, then the loading time skew is minimized, but the device complexity increases
Solution Approach 1:
Multiple pass transistor groups are merged into a single adjacently disposed unit with an odd number of groups. This merging approach consolidates the pass transistor arrangement into a compact configuration that reduces wiring resistance and minimizes loading time skew. By combining multiple functional elements into a unified structure, the design achieves improved performance without proportionally increasing device complexity.
Data Source
AI summary
A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.