Memory Patch Table for Row Neighborhood Repair
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Solution Overview
Problem
In memory arrays, data stored in one row can become unreadable due to defects in adjacent rows, especially in antifuse-based memory cells, causing short circuits and rendering previously stored data inaccessible, which existing redundancy mechanisms struggle to address effectively.
Innovation Solution
A memory device with a patch table mechanism that stores data from affected rows in a temporary cache, writes this data to a repair area, and updates a patch table with addresses for redirecting read/write operations to ensure data integrity by remapping rows with defects to alternative rows in a repair area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy mechanisms are built into the memory device to repair defective rows, then data reliability is improved, but device complexity increases due to the need for additional repair areas and patch tables
Solution Approach 1:
The memory device is segmented into distinct functional areas: normal data storage area, repair area, and patch table area. This segmentation allows the system to isolate defective rows and redirect access to repair rows without affecting the overall memory operation, thereby improving reliability while managing complexity through structured organization.
Solution Approach 2:
The patch table acts as an intermediary data structure that maps defective row addresses to corresponding repair row addresses. This intermediary mechanism enables automatic redirection of read/write operations without requiring complex control logic, thus improving reliability while minimizing the increase in device complexity.
2Reliability
If data from neighboring rows is stored in temporary cache before writing to repair area, then data integrity is improved, but loss of time occurs during the repair process
Solution Approach 1:
Data from defective rows and their neighboring rows is preliminarily stored in a temporary cache area before being written to the repair area. This preliminary action ensures that all necessary data is captured and preserved with full integrity before the actual repair operation, preventing any data loss during the repair process.
Solution Approach 2:
The patent merges multiple data preservation actions into a single repair operation: capturing data from the defective row, capturing data from neighboring rows that may be affected, storing all in temporary cache, and writing to repair area in one coordinated process. This merging reduces the total repair time compared to handling each row separately.
3Ease of operation
If patch table stores addresses of affected rows for remapping, then ease of operation is improved, but device complexity increases due to additional storage requirements
Solution Approach 1:
The patch table stores copied address information mapping defective rows to repair rows. Instead of implementing complex real-time detection and redirection logic, the system creates a static copy of the address mapping in the patch table that can be consulted during normal operations. This copying approach simplifies the access mechanism while incurring minimal additional storage overhead.
Solution Approach 2:
The patch table is preliminarily populated with address mappings during or after the repair process, before normal operations begin. This preliminary population of the patch table eliminates the need for complex runtime analysis of defective rows, allowing the memory controller to simply consult the pre-computed patch table for address redirection, thereby improving ease of operation.
Data Source
AI summary
A memory device for repairing a neighborhood of rows in a memory array using a patch table is disclosed. In one embodiment, circuitry in the memory device is operative to store, in a temporary storage area of the memory device, (i) first data to be stored in row N in the memory array, (ii) second data, if any, stored in row N−1 in the memory array, and (iii) third data, if any, stored in row N+1 in the memory array. The circuitry is operative to write the first data in row N in the memory array, and, in response to an error in writing the first data, to write the first data, the second data, if any, and the third data, if any, in respective rows in a repair area in the memory device. The circuitry is further operative to add the addresses of rows N−1, N, and N+1 to a table stored in the memory device.