Semiconductor Memory Path Circuit Error Detection
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Solution Overview
Problem
Semiconductor memory systems with three-dimensional structures face data transmission errors due to signal degradation across multiple chips, necessitating effective error detection mechanisms to ensure reliable data transfer.
Innovation Solution
Incorporating a semiconductor memory system with multiple path circuits and error detection circuits that utilize parity bits to generate pre-error detection signals, allowing for selective output of error signals and precise error location identification during data transmission through through electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple chips are stacked in a three-dimensional structure to increase integration density, then the degree of integration is improved, but data transmission errors occur due to signal degradation through through electrodes
Solution Approach 1:
The patent segments the data transmission path into multiple independent path circuits, each with dedicated error detection circuits. This segmentation allows individual monitoring of each transmission path through through electrodes, enabling precise error localization without compromising the integrated three-dimensional structure.
Solution Approach 2:
The patent introduces error detection circuits and parity bit mechanisms as intermediary elements between the stacked chips. These intermediaries monitor and detect signal degradation in real-time during data transmission through through electrodes, providing error detection capability without altering the fundamental three-dimensional stacked architecture.
2Reliability
If error detection circuits are added to detect data transmission errors through through electrodes, then data transmission reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements error detection circuits with local quality by assigning specific detection functions to specific path circuits. Each error detection circuit is tailored to monitor its corresponding path circuit's transmission through through electrodes, reducing overall system complexity through specialized local monitoring rather than a monolithic complex detection system.
Solution Approach 2:
The patent applies preliminary action by generating parity bits before data transmission through through electrodes. This pre-computed error detection information is transmitted alongside the data, enabling error detection without requiring complex real-time analysis during transmission, thus simplifying the overall circuit design.
3Productivity
If multiple path circuits are used to transmit data between stacked chips, then data transmission capacity is improved, but the likelihood of transmission errors increases
Solution Approach 1:
The patent segments the multi-path data transmission system into independent path circuits, each with its own error detection circuit. This segmentation enables parallel data transmission across multiple paths while maintaining individual error monitoring capability, thus preserving transmission capacity while managing error rates through targeted detection.
Solution Approach 2:
The patent implements feedback mechanisms where error detection circuits continuously monitor data transmission through through electrodes and generate error detection signals. This feedback enables real-time identification of transmission errors in specific path circuits, allowing for error correction or retransmission while maintaining overall system productivity through parallel operation of multiple paths.
Data Source
AI summary
A semiconductor memory includes a plurality of path circuits for transmitting data inputted from an exterior source or device to a chip. The semiconductor memory is configured to generate a plurality of pre-error detection signals by detecting whether data transmitted between the plurality of path circuits have errors, and selectively output the plurality of pre-error detection signals.