Memory System Command Data Path Error Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems often fail to detect errors or faults in the data path, leading to potential data corruption even when data is written to or read from a memory device.
Innovation Solution
A memory system is configured to detect errors or faults in the data path by generating parity bits associated with data units received from a host device, performing error detection operations, and generating protocol units and data storage units with included parity bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection operations are performed using parity bits in the data path, then reliability is improved, but device complexity increases
Solution Approach 1:
Parity bits are generated in advance and embedded within data units before they are transmitted through the data path. This preliminary action allows error detection to occur automatically during normal operation without requiring additional complex control logic to manage error checking separately.
Solution Approach 2:
The data units carry their own error detection information (parity bits) embedded within them. When data units are received, the system performs error detection by comparing the embedded parity bits with newly calculated parity bits, allowing the data path to self-verify integrity without external intervention or complex control mechanisms.
2Measurement precision
If parity bits are generated and embedded in data units, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The error detection function is merged with the existing data transmission protocol by embedding parity bits directly within the data units themselves. This integration allows error checking to occur as part of the normal data processing flow rather than as a separate time-consuming operation, maintaining measurement precision while minimizing additional processing time.
Data Source
AI summary
Methods, systems, and devices for command and data path error protection are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.