Memory Module Data Path Reconfiguration for Unused Bandwidth
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory modules often have unused data paths that contribute to power consumption due to excess bandwidth, leading to inefficient power usage and potential error detection issues from disabled features like ECC and CRC.
Innovation Solution
A configurable data path mechanism that allows disabling portions of the data path in response to host commands or configuration, including disabling ECC and CRC features, to manage unused data paths and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the data path width is increased to provide excess bandwidth, then data transfer capacity is improved, but power consumption increases due to unused data paths
Solution Approach 1:
The patent implements dynamic configurability of the data path width through mode register settings that allow the memory device to adjust its operational data path width (e.g., between x16 and x8 modes). This enables the system to adapt the data path configuration to actual application needs, activating only the necessary number of data bits and disabling unused portions to reduce power consumption while maintaining adequate data transfer capacity.
2Reliability
If ECC and CRC features are enabled for error detection, then reliability is improved, but false error detections occur when data paths are disabled
Solution Approach 1:
The patent applies preliminary action by configuring the mode register before normal memory operations begin. The mode register settings pre-establish which data bits are valid and which are disabled, allowing the ECC and CRC logic to be properly configured in advance. This prevents false error detections by ensuring that error checking is performed only on actively used data paths, rather than attempting to check disabled or unused data bits.
Data Source
AI summary
Systems and methods are described to enable a memory device integrated in a memory module or system to disable one or more data bits, nibbles or bytes of the memory device. The memory device can be further configured to disable error or redundancy checking associated with the disabled data bits, nibbles or bytes, to mask errors associated with the disabled data bits, nibbles or bytes, and/or to suppress the refresh of portions of a memory array associated with the disabled data bits, nibbles or bytes.