Semiconductor Memory Device Pattern Flag Read Voltage Adjustment
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Solution Overview
Problem
Semiconductor memory devices face challenges in accurately reading data due to interference from neighboring memory cells, leading to errors and inefficiencies in data retrieval.
Innovation Solution
A semiconductor memory device that generates pattern flag data using least significant bit (LSB) and most significant bit (MSB) data from neighboring memory cells, allowing for the adjustment of read voltage to minimize interference and improve data reading accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If data is read from memory cells using a fixed read voltage, then the reading operation is simple and fast, but data accuracy deteriorates due to interference from neighboring memory cells
Solution Approach 1:
The patent applies preliminary action by reading data from neighboring memory cells before reading the target memory cell. The read voltages for neighboring cells are applied in advance, and their data is used to generate a pattern flag that predicts interference effects. This allows the system to prepare compensation information before the actual data reading, improving accuracy without significantly increasing overall operation complexity.
Solution Approach 2:
The patent implements feedback by using the data read from neighboring memory cells to generate a pattern flag, which then feeds back to adjust the read voltage for the target memory cell. This feedback mechanism allows the system to dynamically compensate for interference effects based on the actual state of neighboring cells, thereby improving data reading accuracy while maintaining operational simplicity.
2Measurement precision
If interference compensation is performed using data from all neighboring memory cells, then data accuracy improves, but the amount of data to be processed and transmitted increases
Solution Approach 1:
The patent applies the taking out principle by extracting only the essential information needed for interference compensation. Instead of processing all neighboring cell data, the system generates a compact pattern flag that captures the critical interference characteristics. This extracted flag contains sufficient information for voltage adjustment while significantly reducing the data volume that needs to be transmitted and processed.
Solution Approach 2:
The patent changes the parameter representation by transforming raw neighboring cell data into a pattern flag parameter. This parameter transformation condenses multiple data bits into a compact representation that preserves the essential interference information. The pattern flag serves as an efficient parameter that enables accurate interference compensation without requiring transmission of the full neighboring cell data set.
3Measurement precision
If read voltage is adjusted based on neighboring cell data, then interference effects are reduced and data accuracy improves, but the reading operation time increases
Solution Approach 1:
The patent minimizes time loss by performing the interference compensation preparation in advance. The read voltages for neighboring cells are applied before the target cell reading, and the pattern flag is generated during this preliminary phase. This timing arrangement allows the system to prepare compensation information without extending the critical path of the data reading operation, thus maintaining fast read speeds while improving accuracy.
Solution Approach 2:
The patent employs periodic action by structuring the read operation in distinct phases: first applying read voltages to neighboring cells, then using the generated pattern flag to adjust and apply the read voltage to the target cell. This periodic, phased approach organizes the multi-step process into efficient time segments, allowing interference compensation to be performed systematically without excessive time penalty.
Data Source
AI summary
Provided are a semiconductor memory device, a memory system including the same, and an operating method thereof. The semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit suitable for reading least significant bit data and most significant bit data of neighboring memory cells adjacent to selected memory cells out of the plurality of memory cells, and generating pattern flag data using the least significant bit data and the most significant bit data and a control logic suitable for controlling the peripheral circuit to set a read voltage to be applied to the selected memory cells based on the pattern flag data.