Memory Data Output Circuit for Pattern Reads Without Cell Access

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing semiconductor memory devices, such as SDRAMs, incur increased power consumption and operation duration during special read operations due to the need for accessing memory cells for data patterns, even when normal data is not stored, which affects performance and efficiency.

Innovation Solution

A semiconductor memory device with a data output circuit that outputs fixed data patterns during special read operations without accessing memory cells, thereby reducing power consumption and operation duration by utilizing a multi-purpose register and output control circuit to manage read operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memory cells are accessed during special read operations to output data patterns, then data patterns can be output, but power consumption increases and operation duration increases

Engineering Contradiction:
Improveoperation durationVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent extracts the data pattern storage function from the memory cell array and places it in a dedicated storage unit. During special read operations, only the storage unit is accessed to output data patterns, while memory cell access is eliminated. This extraction resolves the contradiction by removing the harmful energy consumption and time delay associated with accessing memory cells for special read operations.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a storage unit as an intermediary component between the memory cell array and the data output circuit. This storage unit specifically stores data patterns and serves as a dedicated buffer for special read operations. By using this intermediary, the system avoids direct access to memory cells during special reads, thereby reducing power consumption and operation duration while still enabling data pattern output.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If memory cells are accessed during special read operations, then data patterns can be read, but the operation takes longer time

Engineering Contradiction:
ImprovespeedVSAvoidoperation duration
Core Design Contradiction:
ProductivityVSDuration of action of moving object

Solution Approach 1:

The patent extracts the data pattern storage function from the memory cell array and places it in a dedicated storage unit. During special read operations, only the storage unit is accessed to output data patterns, while memory cell access is eliminated. This extraction resolves the contradiction by removing the harmful energy consumption and time delay associated with accessing memory cells for special read operations.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs preliminary action by pre-storing data patterns in the storage unit before they are needed. The storage unit is configured to hold data patterns in advance, so when a special read operation is initiated, the data patterns are already available and can be output immediately without requiring time-consuming access to the memory cell array. This preliminary preparation reduces operation duration and increases speed.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8625364B2Semiconductor memory devices and systems including data output circuits to output stored data during first output mode and output programmed data pattern during second output mode
Publication Date: 2014.01.07 SAMSUNG ELECTRONICS CO LTD
  • US8625364B2 patent drawing
  • US8625364B2 patent drawing
  • US8625364B2 patent drawing

AI summary

According to example embodiments, a semiconductor memory device includes a memory cell array, a multi-purpose register, a data output circuit, and a mode register. The memory cell array is configured to store data. The multi-purpose register is configured to store a data pattern. The data output circuit is configured to output the stored data during a first output mode and output the stored data pattern during a second output mode. The mode register is configured to set the first or second output mode according to a logic level of a portion of a content of the mode register.