Memory Device PCIe Virtual Link for TCP/IP Host Communication

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Solution Overview

Problem

Existing data communication between memory devices and external host devices is limited by reliance on physical connections and lacks scalability and flexibility, particularly in systems utilizing Peripheral Component Interconnect Express (PCIe) infrastructure.

Innovation Solution

Establishing a virtual communication link or network between memory devices and host devices using PCIe protocols, allowing for bidirectional data transfer of TCP/IP or UDP packets, independent of storage protocols like NVMe, and incorporating a data processor to convert payload data between TCP/IP and PCIe formats.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If physical connections are used for data communication between memory devices and host devices, then reliable data transfer is achieved, but scalability and flexibility are limited

Engineering Contradiction:
Improvescalability and flexibilityVSAvoiddata transfer reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent introduces a virtual communication link as an intermediary layer between the physical PCIe connection and the data communication protocol. This virtual link allows TCP/IP packets to be transmitted over PCIe infrastructure without requiring physical cable changes, thereby maintaining reliability while improving scalability and flexibility. The virtual link acts as a mediator that translates between different protocol requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If storage protocols like NVMe are used for communication, then efficient data access is achieved, but protocol dependency reduces versatility

Engineering Contradiction:
Improvedata access efficiencyVSAvoidprotocol independence
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent segments the communication protocol into distinct layers: the physical PCIe transport layer and the application-layer TCP/IP protocol. By separating these functions, the system can maintain efficient PCIe-based data access while simultaneously supporting standard TCP/IP communication. This segmentation allows different protocol stacks to operate independently, improving both efficiency and versatility.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The virtual communication link is designed to be universal, supporting both storage protocols (NVMe) and general-purpose networking protocols (TCP/IP) over the same PCIe infrastructure. This multi-functionality allows the system to achieve efficient data access when needed while maintaining protocol independence for broader compatibility and versatility.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If dedicated communication infrastructure is established, then communication reliability is improved, but system complexity increases

Engineering Contradiction:
Improvecommunication reliabilityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the communication functionality into the existing PCIe infrastructure by creating a virtual link, rather than establishing a separate dedicated physical infrastructure. This combining approach maintains communication reliability through the proven PCIe protocol while avoiding the increased complexity that would result from adding separate hardware layers. The virtual link leverages existing system resources.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20260037454A1Communication between a computing element of a memory device and an electronic device
Publication Date: 2026.02.05 SK HYNIX NAND PRODUCT SOLUTIONS CORP
  • US20260037454A1 patent drawing
  • US20260037454A1 patent drawing
  • US20260037454A1 patent drawing

AI summary

This application is directed to creating a communication link between computing elements of memory devices and host device(s). A memory device includes an input/output data interface configured to couple to a data bus and communicate data via the data bus. A memory device further includes a data processor coupled to the input/output data interface. The data processor has a device IP address. The data processor is configured to generate first payload data having a TCP/IP packet format. The first payload data includes at least one of the device IP address of the data processor and a target IP address of a host device. The data processor is further configured to convert the first payload data to output data having a PCIe packet format. The data processor is further configured to provide the output data to the input/output data interface for communicating the output data via the data bus.