Memory Device Processing Element Bank Segmentation Refresh
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Solution Overview
Problem
Current memory devices lack efficient mechanisms to manage computational operations within the memory system, leading to performance degradation due to the need for periodic refresh operations in DRAM cells, which can hinder the activation of multiple wordlines and impact data operation speed.
Innovation Solution
A memory device with a memory cell array and Processing Elements (PEs) connected to multiple banks, where a control logic activates wordlines and controls refresh operations based on a PE enable signal, allowing for selective activation of banks and simultaneous data operations during refresh cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed periodically on DRAM cells, then data retention is maintained, but data operation speed deteriorates due to inability to activate multiple wordlines simultaneously
Solution Approach 1:
The memory device is divided into multiple banks (first bank, second bank, etc.), each capable of independent refresh operations. This segmentation allows different banks to be refreshed at different times, enabling simultaneous wordline activation in banks not undergoing refresh, thus maintaining both data retention and operational speed.
Solution Approach 2:
The patent implements periodic refresh operations on different banks at different time intervals. By scheduling refresh operations periodically across multiple banks rather than continuously on all banks, the system maintains data retention while allowing other banks to perform computational operations simultaneously.
2Speed
If multiple wordlines are activated simultaneously for computational operations, then data operation speed improves, but refresh operation efficiency deteriorates
Solution Approach 1:
By dividing the memory into multiple banks, the system can activate multiple wordlines in banks not undergoing refresh while performing refresh operations on other banks simultaneously. This segmentation enables parallel refresh and computational operations across different banks.
Solution Approach 2:
The system maintains continuous useful action by performing computational operations in banks not undergoing refresh while simultaneously performing refresh operations in other banks. This continuity is achieved through the multi-bank architecture that allows overlapping refresh and computational activities.
3Reliability
If refresh operations are performed on all banks simultaneously, then data retention is maintained, but computational operation performance deteriorates
Solution Approach 1:
The memory device is segmented into multiple banks that can be refreshed independently. This allows the system to perform refresh operations on only some banks while maintaining computational operations in other banks, thus preserving both data retention and computational performance.
Solution Approach 2:
Instead of performing refresh operations on all banks simultaneously, the system implements periodic refresh operations on different banks at different times. This periodic approach ensures data retention while allowing computational operations to continue in banks not undergoing refresh.
Data Source
AI summary
A memory device according to some aspects of the inventive concepts includes a memory cell array including a plurality of banks, at least one Processing Element (PE) connected to at least one bank selected from the plurality of banks, and a control logic configured to control an active operation in which wordlines included in each of the plurality of banks is activated, and configured to control a refresh operation in which at least one bank is refreshed, based on a PE enable signal configured to selectively enable the at least one PE.