Semiconductor Memory System Peak Current Control
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Solution Overview
Problem
NAND flash memory devices face challenges in reducing peak current during write operations, which can lead to disconnection issues and reliability problems, especially in multi-chip packages and memory cards, where overlapping peak currents can occur, necessitating a solution to enhance write performance and reduce current consumption without increasing circuit complexity.
Innovation Solution
A semiconductor memory system comprising two semiconductor memory devices connected via a common communication line and a control circuit that manages current levels, allowing one device to operate while the other is in a wait state, and includes a voltage generation circuit to supply voltage to the devices, thereby controlling program and verify operations to minimize peak current generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor memory chips are operated simultaneously in a multi-chip package, then storage capacity increases, but peak current overlaps causing disconnection and reliability issues
Solution Approach 1:
The control circuit operates multiple memory chips in an alternating periodic manner, where one chip is in active operation while another is in wait state, then switches roles. This periodic switching prevents simultaneous peak current generation from multiple chips, avoiding disconnection issues while maintaining high storage capacity through multi-chip configuration.
2Manufacturing precision
If program operation is performed with gradual voltage stepping to achieve threshold distribution, then write accuracy improves, but write time increases
Solution Approach 1:
The control circuit performs preliminary preparation by placing memory chips in appropriate initial states before write operations. By pre-positioning chips in wait state or active state based on operation requirements, the system optimizes the write sequence to reduce the number of voltage stepping iterations needed, thereby decreasing write time while maintaining threshold distribution accuracy.
3Reliability
If all bit lines are charged for program and verify operations, then data integrity is ensured, but large peak current is generated
Solution Approach 1:
The control circuit implements periodic operation where only one memory chip performs program and verify operations at a time while others remain in wait state. This temporal separation ensures that bit lines are fully charged for data integrity in the active chip without generating overlapping peak currents from multiple chips, thereby reducing overall peak current consumption.
Data Source
AI summary
A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.