Memory Peripheral Circuit Redundancy Column Control
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Solution Overview
Problem
Conventional memory devices using metal fuses for redundancy column operations face challenges in restoring the pre-redundancy state and are not suitable for miniaturized designs due to space requirements.
Innovation Solution
A memory peripheral circuit with a redundancy column data circuit and column selection control circuit that disables bad column addresses and enables redundancy column addresses, allowing for restoration of the pre-redundancy state without the need for metal fuses, thereby reducing layout space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal fuse is used to disable bad column address, then the bad column can be disabled, but the layout space increases and the state cannot be restored
Solution Approach 1:
The patent extracts the redundancy column information storage function from the traditional metal fuse approach and relocates it to the redundancy column data circuit. This extraction eliminates the need for physical metal fuses in each column decoder, thereby reducing layout space while maintaining the bad column disable function. The redundancy column data circuit stores the bad column address information, replacing the need for destructive metal fuse operations.
Solution Approach 2:
The patent creates a copy of the column decoder functionality within the redundancy column data circuit and column selection control circuit. Instead of using physical metal fuses to disable columns, the system uses logical copying of column address information into the redundancy column data circuit, which can then be used to selectively enable or disable columns through logical operations rather than physical destruction.
2Reliability
If metal fuse is burned out to disable bad column, then the bad column is disabled, but the pre-redundancy state cannot be restored
Solution Approach 1:
The patent transforms the static, irreversible metal fuse disable mechanism into a dynamic, reversible logical control system. The column selection control circuit can dynamically change the enable/disable state of columns based on the stored redundancy column information without permanent physical changes. This allows the system to switch between different operational states (normal mode, redundancy mode, and pre-redundancy restoration mode) as needed.
Solution Approach 2:
The patent enables the recovery of the pre-redundancy state by storing the original column address information in the redundancy column data circuit. When restoration is needed, the system discards the redundancy configuration and recovers the original column mapping by clearing or resetting the redundancy column data, thereby restoring the memory to its state before the bad column was identified without any permanent damage.
3Reliability
If metal fuse is applied in miniaturized memory devices, then the bad column can be disabled, but the space requirement becomes problematic
Solution Approach 1:
The patent merges the redundancy column information storage function with the existing memory peripheral circuits. The redundancy column data circuit is integrated into the memory device's existing architecture, combining multiple functions (data storage, column selection control, and redundancy management) into a unified circuit structure. This integration eliminates the need for separate metal fuse elements and reduces the overall space requirement, making the solution compatible with miniaturized memory devices.
Data Source
AI summary
A memory device and a memory peripheral circuit are provided. The memory peripheral circuit includes a redundancy column data circuit and a column selection control circuit. The redundancy column data circuit is configured to provide a redundancy test mode data signal and a column address signal. The column address signal includes a redundancy column address signal. The column selection control circuit includes a column decoder and a redundancy column decoder. The column decoder disables a bad column address of a main memory block according to the redundancy test mode data signal and the redundancy column address signal. The redundancy column decoder latches the redundancy column address signal, compares the column address signal with the latched redundancy column address to obtain a comparison result, and enables a redundancy column address of a redundancy memory block according to the comparison result.