3D Memory Peripheral Circuit Stacking for Higher Integration
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Solution Overview
Problem
In three-dimensional non-volatile memory devices, the increasing number of stacked word lines leads to a reduction in the cell region area, while the peripheral circuit region area remains unchanged, resulting in inefficient space utilization and hindering high-integration design due to increased waste space.
Innovation Solution
The memory device incorporates a peripheral circuit region that partially overlaps the cell region, featuring multiple vertically stacked sub-peripheral circuit regions, including substrates and circuit elements, to reduce the overall area occupied by the peripheral circuit when viewed on a plane.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked word lines is increased to achieve higher storage capacity, then the cell region area is reduced, but the peripheral circuit region area remains unchanged, resulting in increased waste space and reduced integration efficiency
Solution Approach 1:
The peripheral circuit region is configured to extend in the vertical direction (thickness direction) rather than occupying additional planar area. Multiple peripheral circuits are stacked vertically at different height levels, allowing the peripheral circuit region to overlap with the cell region when viewed in plan view. This vertical stacking approach reduces the planar footprint of the peripheral circuit region while maintaining full functionality of all peripheral circuits.
2Area of moving object
If the peripheral circuit region area is reduced to improve space utilization, then the functionality and reliability of peripheral circuits may be compromised
Solution Approach 1:
The peripheral circuit region is divided into multiple height levels (first height level, second height level, third height level, etc.), with different peripheral circuits disposed at different levels. Each level contains specific peripheral circuits that are electrically connected through conductive structures extending vertically. This segmentation allows each peripheral circuit to have adequate space for its components while the overall region occupies reduced planar area due to vertical stacking.
Solution Approach 2:
Peripheral circuits are nested vertically within the same planar footprint. The first peripheral circuit is disposed at the first height level, the second peripheral circuit at the second height level, and so on, with each circuit containing its own transistors, capacitors, and conductive structures. These nested circuits share the same lateral space but are separated vertically by insulating layers and connected through vertical conductive paths.
Data Source
AI summary
A semiconductor device, and more particularly, to a memory device having a three-dimensional structure are provided. The memory device various example embodiments includes a cell region and a peripheral circuit region that at least partially overlaps the cell region when viewed in plan view. The peripheral circuit region includes a first sub-peripheral circuit region including a substrate and a circuit element on the substrate, and a second sub-peripheral circuit region that is stacked on the first sub-peripheral circuit region in a vertical direction and that includes a sub-poly structure and a circuit element on the sub-poly structure.